luke
/
abc
mirror of https://github.com/YosysHQ/abc.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Assembling timing/hierarchy manager from input data.

This commit is contained in:
Alan Mishchenko 2012-12-15 17:39:34 -08:00
parent 82050bbe11
commit bfad654205
4 changed files with 133 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

49
src/aig/gia/giaAiger.c
View File

@ -504,7 +504,7 @@ Gia_Man_t * Gia_AigerReadFromMemory( char * pContents, int nFileSize, int fSkipS
if ( *pCur == 'a' )
{
pCur++;
vStr = Vec_StrStart( Gia_AigerReadInt(pCur) ); pCur += 4;
vStr = Vec_StrStart( Gia_AigerReadInt(pCur) ); pCur += 4;
memcpy( Vec_StrArray(vStr), pCur, Vec_StrSize(vStr) );
pCur += Vec_StrSize(vStr);
pNew->pAigExtra = Gia_AigerReadFromMemory( Vec_StrArray(vStr), Vec_StrSize(vStr), 0, 0 );
@ -514,18 +514,23 @@ Gia_Man_t * Gia_AigerReadFromMemory( char * pContents, int nFileSize, int fSkipS
else if ( *pCur == 'c' )
{
pCur++;
assert( Gia_AigerReadInt(pCur) == 4 ); pCur += 4;
pNew->nConstrs = Gia_AigerReadInt( pCur ); pCur += 4;
assert( Gia_AigerReadInt(pCur) == 4 ); pCur += 4;
pNew->nConstrs = Gia_AigerReadInt( pCur ); pCur += 4;
}
// read delay information
else if ( *pCur == 'd' )
else if ( *pCur == 'i' )
{
pCur++;
assert( Gia_AigerReadInt(pCur) == 4*(Gia_ManPiNum(pNew) + Gia_ManPoNum(pNew)) ); pCur += 4;
pNew->vInArrs = Vec_FltStart( Gia_ManPiNum(pNew) );
pNew->vOutReqs = Vec_FltStart( Gia_ManPoNum(pNew) );
memcpy( Vec_FltArray(pNew->vInArrs), pCur, 4*Gia_ManPiNum(pNew) ); pCur += 4*Gia_ManPiNum(pNew);
memcpy( Vec_FltArray(pNew->vOutReqs), pCur, 4*Gia_ManPoNum(pNew) ); pCur += 4*Gia_ManPoNum(pNew);
nInputs = Gia_AigerReadInt(pCur)/4; pCur += 4;
pNew->vInArrs = Vec_FltStart( nInputs );
memcpy( Vec_FltArray(pNew->vInArrs), pCur, 4*nInputs ); pCur += 4*nInputs;
}
else if ( *pCur == 'o' )
{
pCur++;
nOutputs = Gia_AigerReadInt(pCur)/4; pCur += 4;
pNew->vOutReqs = Vec_FltStart( nOutputs );
memcpy( Vec_FltArray(pNew->vOutReqs), pCur, 4*nOutputs ); pCur += 4*nOutputs;
}
// read equivalence classes
else if ( *pCur == 'e' )
@ -677,6 +682,8 @@ Gia_Man_t * Gia_AigerReadFromMemory( char * pContents, int nFileSize, int fSkipS
Tim_ManPrint( pNew->pManTime );
Tim_ManCreate( pNew->pManTime, Abc_FrameReadLibBox(), pNew->vInArrs, pNew->vOutReqs );
Tim_ManPrint( pNew->pManTime );
Vec_FltFreeP( &pNew->vInArrs );
Vec_FltFreeP( &pNew->vOutReqs );
}
/*
@ -1047,14 +1054,24 @@ void Gia_AigerWrite( Gia_Man_t * pInit, char * pFileName, int fWriteSymbols, int
}
*/
// write gate classes
if ( p->vInArrs && p->vOutReqs )
if ( p->pManTime )
{
fprintf( pFile, "d" );
Gia_FileWriteBufferSize( pFile, 4*(Gia_ManPiNum(p) + Gia_ManPoNum(p)) );
assert( Vec_FltSize(p->vInArrs) == Gia_ManPiNum(p) );
assert( Vec_FltSize(p->vOutReqs) == Gia_ManPoNum(p) );
fwrite( Vec_FltArray(p->vInArrs), 1, 4*Gia_ManPiNum(p), pFile );
fwrite( Vec_FltArray(p->vOutReqs), 1, 4*Gia_ManPoNum(p), pFile );
Vec_Flt_t * vArrTimes, * vReqTimes;
if ( Tim_ManGetArrsReqs( p->pManTime, &vArrTimes, &vReqTimes ) )
{
fprintf( pFile, "i" );
Gia_FileWriteBufferSize( pFile, 4*Tim_ManPiNum(p->pManTime) );
assert( Vec_FltSize(vArrTimes) == Tim_ManPiNum(p->pManTime) );
fwrite( Vec_FltArray(vArrTimes), 1, 4*Gia_ManPiNum(p->pManTime), pFile );
fprintf( pFile, "o" );
Gia_FileWriteBufferSize( pFile, 4*Tim_ManPoNum(p->pManTime) );
assert( Vec_FltSize(vReqTimes) == Tim_ManPoNum(p->pManTime) );
fwrite( Vec_FltArray(vReqTimes), 1, 4*Gia_ManPoNum(p->pManTime), pFile );
Vec_FltFree( vArrTimes );
Vec_FltFree( vReqTimes );
}
}
// write equivalences
if ( p->pReprs && p->pNexts )

53
src/base/abci/abcTim.c
View File

@ -224,6 +224,36 @@ Vec_Ptr_t * Abc_NtkTestTimCollectCone( Abc_Ntk_t * pNtk, Abc_Obj_t * pObj )
}
/**Function*************************************************************
Synopsis [Create arrival times]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Flt_t * Abc_NtkTestCreateArrivals( int nInputs )
{
Vec_Flt_t * p;
int i;
p = Vec_FltAlloc( nInputs );
for ( i = 0; i < nInputs; i++ )
Vec_FltPush( p, 1.0*(i % 10) );
return p;
}
Vec_Flt_t * Abc_NtkTestCreateRequired( int nOutputs )
{
Vec_Flt_t * p;
int i;
p = Vec_FltAlloc( nOutputs );
for ( i = 0; i < nOutputs; i++ )
Vec_FltPush( p, 100.0 + 1.0*i );
return p;
}
/**Function*************************************************************
Synopsis [Derives GIA manager together with the hierachy manager.]
@ -241,7 +271,8 @@ Gia_Man_t * Abc_NtkTestTimDeriveGia( Abc_Ntk_t * pNtk, int fVerbose )
Gia_Man_t * pGia = NULL;
Gia_Man_t * pHoles = NULL;
Tim_Man_t * pTim = NULL;
Vec_Int_t * vGiaCoLits;
Vec_Int_t * vGiaCoLits, * vGiaCoLits2;
Vec_Flt_t * vArrTimes, * vReqTimes;
Abc_Obj_t * pObj, * pFanin;
int i, k, Entry, curPi, curPo, BoxUniqueId;
int nBoxFaninMax = 0;
@ -283,6 +314,7 @@ Gia_Man_t * Abc_NtkTestTimDeriveGia( Abc_Ntk_t * pNtk, int fVerbose )
pObj->iTemp = Abc_Var2Lit( Gia_ObjId(pGia, Gia_ManCi(pGia, curPi++)), 0 );
// create internal nodes in a topologic order from white boxes
vGiaCoLits = Vec_IntAlloc( 1000 );
vGiaCoLits2 = Vec_IntAlloc( 1000 );
Abc_NtkForEachNode( pNtk, pObj, i )
{
if ( !pObj->fMarkA ) // not a white box
@ -309,7 +341,8 @@ Gia_Man_t * Abc_NtkTestTimDeriveGia( Abc_Ntk_t * pNtk, int fVerbose )
// handle box outputs
// save CO drivers for the Holes
Gia_ManAppendCo( pHoles, pObj->iTemp );
Vec_IntPush( vGiaCoLits2, pObj->iTemp );
// Gia_ManAppendCo( pHoles, pObj->iTemp );
// load CO drivers for the AIG
pObj->iTemp = Abc_Var2Lit( Gia_ObjId(pGia, Gia_ManCi(pGia, curPi++)), 0 );
}
@ -320,6 +353,10 @@ Gia_Man_t * Abc_NtkTestTimDeriveGia( Abc_Ntk_t * pNtk, int fVerbose )
Vec_IntForEachEntry( vGiaCoLits, Entry, i )
Gia_ManAppendCo( pGia, Entry );
Vec_IntFree( vGiaCoLits );
// second AIG
Vec_IntForEachEntry( vGiaCoLits2, Entry, i )
Gia_ManAppendCo( pHoles, Entry );
Vec_IntFree( vGiaCoLits2 );
// check parameters
curPo += Abc_NtkPoNum( pNtk );
assert( curPi == Gia_ManPiNum(pGia) );
@ -340,11 +377,19 @@ Gia_Man_t * Abc_NtkTestTimDeriveGia( Abc_Ntk_t * pNtk, int fVerbose )
assert( pGia->pManTime == NULL );
pGia->pManTime = pTim;
// combinen hierarchy manager with box info and input/output arrival/required info
// derive hierarchy manager from box info and input/output arrival/required info
vArrTimes = Abc_NtkTestCreateArrivals( Abc_NtkPiNum(pNtk) );
vReqTimes = Abc_NtkTestCreateRequired( Abc_NtkPoNum(pNtk) );
Tim_ManPrint( pGia->pManTime );
Tim_ManCreate( pGia->pManTime, Abc_FrameReadLibBox(), NULL, NULL );
Tim_ManCreate( pGia->pManTime, Abc_FrameReadLibBox(), vArrTimes, vReqTimes );
Tim_ManPrint( pGia->pManTime );
Vec_FltFree( vArrTimes );
Vec_FltFree( vReqTimes );
Gia_AigerWrite( pHoles, "holes00.aig", 0, 0 );
// return
pGia->pAigExtra = pHoles;
return pGia;

1
src/misc/tim/tim.h
View File

@ -128,6 +128,7 @@ extern Tim_Man_t * Tim_ManLoad( Vec_Str_t * p, int fHieOnly );
extern Tim_Man_t * Tim_ManStart( int nCis, int nCos );
extern Tim_Man_t * Tim_ManDup( Tim_Man_t * p, int fUnitDelay );
extern void Tim_ManCreate( Tim_Man_t * p, void * pLib, Vec_Flt_t * vInArrs, Vec_Flt_t * vOutReqs );
extern int Tim_ManGetArrsReqs( Tim_Man_t * p, Vec_Flt_t ** pvInArrs, Vec_Flt_t ** pvOutReqs );
extern void Tim_ManStop( Tim_Man_t * p );
extern void Tim_ManStopP( Tim_Man_t ** p );
extern void Tim_ManPrint( Tim_Man_t * p );

55
src/misc/tim/timMan.c
View File

@ -186,7 +186,8 @@ void Tim_ManCreate( Tim_Man_t * p, void * pLib, Vec_Flt_t * vInArrs, Vec_Flt_t *
If_LibBox_t * pLibBox = (If_LibBox_t *)pLib;
If_Box_t * pIfBox;
Tim_Box_t * pBox;
float * pTable, Entry;
Tim_Obj_t * pObj;
float * pTable;
int i, k;
assert( p->vDelayTables == NULL );
p->vDelayTables = Vec_PtrStart( Vec_PtrSize(pLibBox->vBoxes) );
@ -227,19 +228,63 @@ void Tim_ManCreate( Tim_Man_t * p, void * pLib, Vec_Flt_t * vInArrs, Vec_Flt_t *
if ( vInArrs )
{
assert( Vec_FltSize(vInArrs) == Tim_ManPiNum(p) );
Vec_FltForEachEntry( vInArrs, Entry, i )
Tim_ManInitPiArrival( p, i, Entry );
Tim_ManForEachPi( p, pObj, i )
pObj->timeArr = Vec_FltEntry(vInArrs, i);
}
// create required times
if ( vOutReqs )
{
k = 0;
assert( Vec_FltSize(vOutReqs) == Tim_ManPoNum(p) );
Vec_FltForEachEntry( vOutReqs, Entry, i )
Tim_ManInitPoRequired( p, i, Entry );
Tim_ManForEachPo( p, pObj, i )
pObj->timeReq = Vec_FltEntry(vOutReqs, k++);
assert( k == Tim_ManPoNum(p) );
}
}
/**Function*************************************************************
Synopsis [Get arrival and required times if they are non-trivial.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Tim_ManGetArrsReqs( Tim_Man_t * p, Vec_Flt_t ** pvInArrs, Vec_Flt_t ** pvOutReqs )
{
Tim_Obj_t * pObj;
int i, fTrivial = 1;
*pvInArrs = NULL;
*pvOutReqs = NULL;
Tim_ManForEachPi( p, pObj, i )
if ( pObj->timeArr != 0.0 )
{
fTrivial = 0;
break;
}
Tim_ManForEachPo( p, pObj, i )
if ( pObj->timeReq != TIM_ETERNITY )
{
fTrivial = 0;
break;
}
if ( fTrivial )
return 0;
*pvInArrs = Vec_FltAlloc( Tim_ManPiNum(p) );
Tim_ManForEachPi( p, pObj, i )
Vec_FltPush( *pvInArrs, pObj->timeArr );
*pvOutReqs = Vec_FltAlloc( Tim_ManPoNum(p) );
Tim_ManForEachPo( p, pObj, i )
Vec_FltPush( *pvOutReqs, pObj->timeReq );
return 1;
}
/**Function*************************************************************
Synopsis [Prints the timing manager.]