mirror of https://github.com/YosysHQ/abc.git
Fixing time primtouts throughout the code.
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4760983a46
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@ -23,6 +23,7 @@
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#include "src/sat/cnf/cnf.h"
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#include "src/sat/bsat/satSolver2.h"
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#include "src/base/main/main.h"
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#include "src/aig/saig/saig.h"
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ABC_NAMESPACE_IMPL_START
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@ -187,7 +188,7 @@ Abc_Cex_t * Gia_ManCexRemap( Gia_Man_t * p, Abc_Cex_t * pCexAbs, Vec_Int_t * vPi
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int Gia_ManGlaRefine( Gia_Man_t * p, Abc_Cex_t * pCex, int fMinCut, int fVerbose )
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{
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extern void Nwk_ManDeriveMinCut( Gia_Man_t * p, int fVerbose );
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extern Abc_Cex_t * Saig_ManCbaFindCexCareBits( Aig_Man_t * pAig, Abc_Cex_t * pCex, int nInputs, int fVerbose );
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// extern Abc_Cex_t * Saig_ManCbaFindCexCareBits( Aig_Man_t * pAig, Abc_Cex_t * pCex, int nInputs, int fVerbose );
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int fAddOneLayer = 1;
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Abc_Cex_t * pCexNew = NULL;
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Gia_Man_t * pAbs;
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@ -84,7 +84,7 @@ static int Ivy_FastMapNodeDeref( Ivy_Man_t * pAig, Ivy_Obj_t * pObj );
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extern clock_t s_MappingTime;
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extern clock_t s_MappingMem;
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extern int s_MappingMem;
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////////////////////////////////////////////////////////////////////////
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@ -37,10 +37,10 @@ ABC_NAMESPACE_IMPL_START
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//extern int s_TotalNodes = 0;
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//extern int s_TotalChanges = 0;
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int s_MappingTime = 0;
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clock_t s_MappingTime = 0;
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int s_MappingMem = 0;
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int s_ResubTime = 0;
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int s_ResynTime = 0;
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clock_t s_ResubTime = 0;
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clock_t s_ResynTime = 0;
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////////////////////////////////////////////////////////////////////////
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/// FUNCTION DEFINITIONS ///
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@ -117,7 +117,7 @@ static Dec_Graph_t * Abc_ManResubDivs3( Abc_ManRes_t * p, int Required );
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static Vec_Ptr_t * Abc_CutFactorLarge( Abc_Obj_t * pNode, int nLeavesMax );
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static int Abc_CutVolumeCheck( Abc_Obj_t * pNode, Vec_Ptr_t * vLeaves );
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extern int s_ResubTime;
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extern clock_t s_ResubTime;
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////////////////////////////////////////////////////////////////////////
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/// FUNCTION DEFINITIONS ///
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@ -684,8 +684,9 @@ char * Io_NtkDeriveSop( Mem_Flex_t * pMem, word uTruth, int nVars, Vec_Int_t * v
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// check the case of constant cover
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if ( Vec_IntSize(vCover) == 0 || (Vec_IntSize(vCover) == 1 && Vec_IntEntry(vCover,0) == 0) )
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{
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char * pStr0 = " 0\n", * pStr1 = " 1\n";
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assert( RetValue == 0 );
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return Vec_IntSize(vCover) == 0 ? " 0\n" : " 1\n";
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return Vec_IntSize(vCover) == 0 ? pStr0 : pStr1;
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}
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// derive the AIG for that tree
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pSop = Abc_SopCreateFromIsop( pMem, nVars, vCover );
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@ -28,7 +28,7 @@ ABC_NAMESPACE_IMPL_START
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static int Fpga_MappingPostProcess( Fpga_Man_t * p );
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extern clock_t s_MappingTime;
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extern clock_t s_MappingMem;
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extern int s_MappingMem;
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////////////////////////////////////////////////////////////////////////
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@ -27,7 +27,7 @@ ABC_NAMESPACE_IMPL_START
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/// DECLARATIONS ///
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////////////////////////////////////////////////////////////////////////
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extern int s_MappingTime;
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extern clock_t s_MappingTime;
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////////////////////////////////////////////////////////////////////////
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/// FUNCTION DEFINITIONS ///
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@ -27,7 +27,7 @@ ABC_NAMESPACE_IMPL_START
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/// DECLARATIONS ///
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////////////////////////////////////////////////////////////////////////
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extern int s_MappingTime;
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extern clock_t s_MappingTime;
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////////////////////////////////////////////////////////////////////////
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/// FUNCTION DEFINITIONS ///
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@ -76,7 +76,7 @@ struct Res_Man_t_
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extern Hop_Obj_t * Kit_GraphToHop( Hop_Man_t * pMan, Kit_Graph_t * pGraph );
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extern int s_ResynTime;
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extern clock_t s_ResynTime;
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////////////////////////////////////////////////////////////////////////
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/// FUNCTION DEFINITIONS ///
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@ -65,7 +65,7 @@ struct Llb_Mnn_t_
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};
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extern int timeBuild, timeAndEx, timeOther;
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extern clock_t timeBuild, timeAndEx, timeOther;
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extern int nSuppMax;
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////////////////////////////////////////////////////////////////////////
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