 Matt Guthaus
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fb17abb16c
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-04-22 10:40:27 -07:00 |
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Matt Guthaus
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14f440df73
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Update golden results with new lib syntax
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2020-04-22 10:40:04 -07:00 |
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mrg
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4d6d6af0a1
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Merge remote-tracking branch 'public/dev' into dev
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2020-04-22 09:28:25 -07:00 |
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 David Ratchkov
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c2419af2e2
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Fix voltage_map names (these do not need to match pg_pin names)
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2020-04-22 09:03:22 -07:00 |
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mrg
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90fdaf902c
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Merge branch 'tech_migration' into dev
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2020-04-20 16:28:16 -07:00 |
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mrg
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dfbf6fe45c
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Default is to use preferred layer directions
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2020-04-20 15:33:53 -07:00 |
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mrg
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8c177f9947
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Split col mux test
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2020-04-20 15:03:32 -07:00 |
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mrg
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7995451cbb
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PEP8 formatting
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2020-04-20 14:45:18 -07:00 |
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mrg
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69d0e5e372
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Split port data test into single and multi-port.
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2020-04-20 14:26:44 -07:00 |
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mrg
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7f65176908
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Configured bitline directions into prot_data
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2020-04-20 14:23:40 -07:00 |
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mrg
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2a9dde5401
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Merge branch 'tech_migration' into dev
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2020-04-20 09:07:36 -07:00 |
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 jcirimel
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32317ce3a5
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Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev
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2020-04-18 14:23:31 -07:00 |
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jcirimel
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f590ecf83c
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fix minimum pinv sizing
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2020-04-18 05:51:21 -07:00 |
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jcirimel
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add9ec7b28
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remove excess newlines
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2020-04-18 05:42:23 -07:00 |
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jcirimel
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85bc801689
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fix pinv drc bug
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2020-04-18 05:34:55 -07:00 |
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jcirimel
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1f094b03bc
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use more optimal discrete pinv sizing
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2020-04-18 05:26:39 -07:00 |
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David Ratchkov
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5aea45ed69
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- Fix switched disabled powers
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2020-04-17 16:23:06 -07:00 |
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David Ratchkov
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123cc371be
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- Fix disabled power char
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2020-04-17 16:09:58 -07:00 |
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jcirimel
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486819ae0d
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fix width bin typo
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2020-04-17 15:27:36 -07:00 |
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David Ratchkov
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1f816e2823
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- Characterize actual disabled power (read mode only)
- Report rise/fall power individually
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2020-04-17 14:55:17 -07:00 |
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jcirimel
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a158ad1e81
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add missing import
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2020-04-17 14:24:52 -07:00 |
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mrg
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cbb67ad483
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Update to run LVS when no DRC errors too.
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2020-04-17 13:57:52 -07:00 |
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David Ratchkov
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7e36cd4828
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- Write voltage_map and pg_pin
- Remove 'when' condition on leakage power
- Remove 'clk*' from 'when' condition on internal_power on the same 'clk*' pin
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2020-04-17 13:45:57 -07:00 |
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mrg
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f1925420cf
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Only allow DRC fail with LVS pass if using Magic.
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2020-04-17 10:30:26 -07:00 |
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mrg
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75fce9894c
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Allow LVS to run even if DRC fails.
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2020-04-17 09:35:07 -07:00 |
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jcirimel
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9316fb8b01
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Merge branch 'dev' into discrete_models
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2020-04-16 16:48:21 -07:00 |
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jcirimel
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ed54c7ab83
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Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev
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2020-04-16 16:48:07 -07:00 |
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mrg
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8ece411954
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Merge branch 'dev' into tech_migration
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2020-04-16 11:32:02 -07:00 |
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mrg
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843e9414df
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Parameterize vdd and gnd pin in write driver array.
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2020-04-16 11:28:35 -07:00 |
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mrg
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770533e7b1
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Parameterize vdd and gnd pin in sense amp array.
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2020-04-16 11:27:26 -07:00 |
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mrg
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d1319d633d
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Don't widen too short wires either
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2020-04-16 11:02:54 -07:00 |
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jcirimel
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24e0e326d4
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merge dev in to disc...
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2020-04-16 02:18:39 -07:00 |
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jcirimel
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ebb1a7bedb
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merge local with dev
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2020-04-16 02:16:56 -07:00 |
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mrg
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b347e3f7a8
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Try both layers for reversed layer stacks.
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2020-04-15 16:49:04 -07:00 |
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mrg
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9d2902de9e
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Conditional well spacing
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2020-04-15 15:55:49 -07:00 |
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mrg
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94eb2afa36
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Change to callable DRC rule. Use bottom coordinate for bus offsets.
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2020-04-15 15:29:55 -07:00 |
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mrg
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e95c97d7a5
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PEP8 cleanup
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2020-04-15 14:29:43 -07:00 |
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mrg
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1564d6e02b
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PEP8 cleanup
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2020-04-15 11:24:28 -07:00 |
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mrg
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43fe1ae023
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Improve pitch computation
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2020-04-15 11:16:45 -07:00 |
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mrg
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331a4f4606
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Fix wire width bug in short jogs. PEP8 cleanup.
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2020-04-15 09:48:42 -07:00 |
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jcirimel
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6c1c72c520
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fix pgates binning off-by-one
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2020-04-15 04:09:58 -07:00 |
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mrg
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0941ebc3da
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Fix well spacing issue
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2020-04-14 14:08:07 -07:00 |
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mrg
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32d190b8b1
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Jog connection on M1 for bank select.
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2020-04-14 12:15:56 -07:00 |
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mrg
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43dcf675a1
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Move pnand outputs to M1. Debug hierarchical decoder multirow.
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2020-04-14 10:52:25 -07:00 |
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jcirimel
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5f4ed47c57
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netlist only discrete simulating
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2020-04-13 20:48:34 -07:00 |
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jcirimel
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afcb5174ac
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discrete dff tests working
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2020-04-11 01:19:04 -07:00 |
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mrg
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2e67d44cd7
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First pass of multiple bitcells per decoder row
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2020-04-10 13:29:41 -07:00 |
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jcirimel
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a0eb9839ad
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revert units on sp_lib, begin discrete tx simulation
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2020-04-09 19:39:21 -07:00 |
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mrg
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7888e54fc4
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Remove dynamic bitcell multiple detection.
Check for decoder bitcell multiple in tech file or assume 1.
PEP8 fixes.
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2020-04-09 11:38:18 -07:00 |
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Matt Guthaus
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75bd2b46a5
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OpenRAM v1.1.5
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2020-04-09 10:02:15 -07:00 |
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