mirror of https://github.com/VLSIDA/OpenRAM.git
Merge remote-tracking branch 'public/dev' into dev
This commit is contained in:
mrg
commit
4d6d6af0a1
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@ -8,3 +8,5 @@
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*.toc
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*.synctex.gz
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**/model_data
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outputs
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technology/freepdk45/ncsu_basekit
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@ -59,7 +59,8 @@ class delay(simulation):
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""" Create measurement names. The names themselves currently define the type of measurement """
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self.delay_meas_names = ["delay_lh", "delay_hl", "slew_lh", "slew_hl"]
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self.power_meas_names = ["read0_power", "read1_power", "write0_power", "write1_power"]
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self.power_meas_names = ["read0_power", "read1_power", "write0_power", "write1_power",
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"disabled_read0_power", "disabled_read1_power", "disabled_write0_power", "disabled_write1_power"]
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# self.voltage_when_names = ["volt_bl", "volt_br"]
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# self.bitline_delay_names = ["delay_bl", "delay_br"]
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@ -108,6 +109,11 @@ class delay(simulation):
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self.read_lib_meas.append(power_measure("read0_power", "FALL", measure_scale=1e3))
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self.read_lib_meas[-1].meta_str = sram_op.READ_ZERO
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self.read_lib_meas.append(power_measure("disabled_read1_power", "RISE", measure_scale=1e3))
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self.read_lib_meas[-1].meta_str = "disabled_read1"
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self.read_lib_meas.append(power_measure("disabled_read0_power", "FALL", measure_scale=1e3))
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self.read_lib_meas[-1].meta_str = "disabled_read0"
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# This will later add a half-period to the spice time delay. Only for reading 0.
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for obj in self.read_lib_meas:
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if obj.meta_str is sram_op.READ_ZERO:
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@ -156,6 +162,11 @@ class delay(simulation):
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self.write_lib_meas.append(power_measure("write0_power", "FALL", measure_scale=1e3))
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self.write_lib_meas[-1].meta_str = sram_op.WRITE_ZERO
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self.write_lib_meas.append(power_measure("disabled_write1_power", "RISE", measure_scale=1e3))
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self.write_lib_meas[-1].meta_str = "disabled_write1"
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self.write_lib_meas.append(power_measure("disabled_write0_power", "FALL", measure_scale=1e3))
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self.write_lib_meas[-1].meta_str = "disabled_write0"
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write_measures = []
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write_measures.append(self.write_lib_meas)
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write_measures.append(self.create_write_bit_measures())
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@ -665,7 +676,7 @@ class delay(simulation):
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if not success:
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feasible_period = 2 * feasible_period
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continue
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# Positions of measurements currently hardcoded. First 2 are delays, next 2 are slews
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feasible_delays = [results[port][mname] for mname in self.delay_meas_names if "delay" in mname]
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feasible_slews = [results[port][mname] for mname in self.delay_meas_names if "slew" in mname]
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@ -1198,6 +1209,9 @@ class delay(simulation):
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write_port)
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self.measure_cycles[write_port][sram_op.WRITE_ZERO] = len(self.cycle_times)-1
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self.add_noop_clock_one_port(write_port)
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self.measure_cycles[write_port]["disabled_write0"] = len(self.cycle_times)-1
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# This also ensures we will have a H->L transition on the next read
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self.add_read("R data 1 address {} to set dout caps".format(inverse_address),
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inverse_address,
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@ -1208,6 +1222,10 @@ class delay(simulation):
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read_port)
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self.measure_cycles[read_port][sram_op.READ_ZERO] = len(self.cycle_times)-1
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self.add_noop_clock_one_port(read_port)
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self.measure_cycles[read_port]["disabled_read0"] = len(self.cycle_times) - 1
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self.add_noop_all_ports("Idle cycle (if read takes >1 cycle)")
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self.add_write("W data 1 address {} to write value".format(self.probe_address),
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@ -1217,12 +1235,19 @@ class delay(simulation):
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write_port)
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self.measure_cycles[write_port][sram_op.WRITE_ONE] = len(self.cycle_times)-1
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self.add_noop_clock_one_port(write_port)
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self.measure_cycles[write_port]["disabled_write1"] = len(self.cycle_times)-1
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self.add_write("W data 0 address {} to clear din caps".format(inverse_address),
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inverse_address,
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data_zeros,
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wmask_ones,
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write_port)
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self.add_noop_clock_one_port(read_port)
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self.measure_cycles[read_port]["disabled_read1"] = len(self.cycle_times) - 1
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# This also ensures we will have a L->H transition on the next read
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self.add_read("R data 0 address {} to clear dout caps".format(inverse_address),
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inverse_address,
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@ -181,17 +181,20 @@ class lib:
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self.lib.write(" dont_touch : true;\n")
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self.lib.write(" area : {};\n\n".format(self.sram.width * self.sram.height))
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#Build string of all control signals.
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self.write_pg_pin()
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#Build string of all control signals.
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control_str = 'csb0' #assume at least 1 port
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for i in range(1, self.total_port_num):
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control_str += ' & csb{0}'.format(i)
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# Leakage is included in dynamic when macro is enabled
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self.lib.write(" leakage_power () {\n")
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self.lib.write(" when : \"{0}\";\n".format(control_str))
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# 'when' condition unnecessary when cs pin does not turn power to devices
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# self.lib.write(" when : \"{0}\";\n".format(control_str))
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self.lib.write(" value : {};\n".format(self.char_sram_results["leakage_power"]))
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self.lib.write(" }\n")
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self.lib.write(" cell_leakage_power : {};\n".format(0))
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self.lib.write(" cell_leakage_power : {};\n".format(self.char_sram_results["leakage_power"]))
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def write_units(self):
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@ -240,6 +243,9 @@ class lib:
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self.lib.write(" default_max_fanout : 4.0 ;\n")
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self.lib.write(" default_connection_class : universal ;\n\n")
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self.lib.write(" voltage_map ( VDD, {} );\n".format(tech.spice["nom_supply_voltage"]))
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self.lib.write(" voltage_map ( GND, 0 );\n\n")
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def create_list(self,values):
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""" Helper function to create quoted, line wrapped list """
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list_values = ", ".join(str(v) for v in values)
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@ -516,42 +522,69 @@ class lib:
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if port in self.write_ports:
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if port in self.read_ports:
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web_name = " & !web{0}".format(port)
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avg_write_power = np.mean(self.char_port_results[port]["write1_power"] + self.char_port_results[port]["write0_power"])
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write1_power = np.mean(self.char_port_results[port]["write1_power"])
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write0_power = np.mean(self.char_port_results[port]["write0_power"])
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self.lib.write(" internal_power(){\n")
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self.lib.write(" when : \"!csb{0} & clk{0}{1}\"; \n".format(port, web_name))
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self.lib.write(" when : \"!csb{0}{1}\"; \n".format(port, web_name))
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self.lib.write(" rise_power(scalar){\n")
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self.lib.write(" values(\"{0}\");\n".format(avg_write_power/2.0))
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self.lib.write(" values(\"{0:.6e}\");\n".format(write1_power))
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self.lib.write(" }\n")
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self.lib.write(" fall_power(scalar){\n")
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self.lib.write(" values(\"{0}\");\n".format(avg_write_power/2.0))
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self.lib.write(" values(\"{0:.6e}\");\n".format(write0_power))
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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# Disabled power.
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disabled_write1_power = np.mean(self.char_port_results[port]["disabled_write1_power"])
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disabled_write0_power = np.mean(self.char_port_results[port]["disabled_write0_power"])
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self.lib.write(" internal_power(){\n")
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self.lib.write(" when : \"csb{0}{1}\"; \n".format(port, web_name))
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self.lib.write(" rise_power(scalar){\n")
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self.lib.write(" values(\"{0:.6e}\");\n".format(disabled_write1_power))
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self.lib.write(" }\n")
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self.lib.write(" fall_power(scalar){\n")
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self.lib.write(" values(\"{0:.6e}\");\n".format(disabled_write0_power))
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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if port in self.read_ports:
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if port in self.write_ports:
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web_name = " & web{0}".format(port)
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avg_read_power = np.mean(self.char_port_results[port]["read1_power"] + self.char_port_results[port]["read0_power"])
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read1_power = np.mean(self.char_port_results[port]["read1_power"])
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read0_power = np.mean(self.char_port_results[port]["read0_power"])
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self.lib.write(" internal_power(){\n")
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self.lib.write(" when : \"!csb{0} & !clk{0}{1}\"; \n".format(port, web_name))
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self.lib.write(" when : \"!csb{0}{1}\"; \n".format(port, web_name))
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self.lib.write(" rise_power(scalar){\n")
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self.lib.write(" values(\"{0}\");\n".format(avg_read_power/2.0))
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self.lib.write(" values(\"{0:.6e}\");\n".format(read1_power))
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self.lib.write(" }\n")
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self.lib.write(" fall_power(scalar){\n")
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self.lib.write(" values(\"{0}\");\n".format(avg_read_power/2.0))
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self.lib.write(" values(\"{0:.6e}\");\n".format(read0_power))
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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# Have 0 internal power when disabled, this will be represented as leakage power.
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self.lib.write(" internal_power(){\n")
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self.lib.write(" when : \"csb{0}\"; \n".format(port))
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self.lib.write(" rise_power(scalar){\n")
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self.lib.write(" values(\"0\");\n")
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self.lib.write(" }\n")
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self.lib.write(" fall_power(scalar){\n")
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self.lib.write(" values(\"0\");\n")
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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# Disabled power.
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disabled_read1_power = np.mean(self.char_port_results[port]["disabled_read1_power"])
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disabled_read0_power = np.mean(self.char_port_results[port]["disabled_read0_power"])
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self.lib.write(" internal_power(){\n")
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self.lib.write(" when : \"csb{0}{1}\"; \n".format(port, web_name))
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self.lib.write(" rise_power(scalar){\n")
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self.lib.write(" values(\"{0:.6e}\");\n".format(disabled_read1_power))
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self.lib.write(" }\n")
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self.lib.write(" fall_power(scalar){\n")
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self.lib.write(" values(\"{0:.6e}\");\n".format(disabled_read0_power))
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self.lib.write(" }\n")
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self.lib.write(" }\n")
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def write_pg_pin(self):
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self.lib.write(" pg_pin(vdd) {\n")
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self.lib.write(" voltage_name : VDD;\n")
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self.lib.write(" pg_type : primary_power;\n")
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self.lib.write(" }\n\n")
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self.lib.write(" pg_pin(gnd) {\n")
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self.lib.write(" voltage_name : GND;\n")
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self.lib.write(" pg_type : primary_ground;\n")
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self.lib.write(" }\n\n")
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def compute_delay(self):
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"""Compute SRAM delays for current corner"""
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self.d = delay(self.sram, self.sp_file, self.corner)
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@ -279,6 +279,23 @@ class simulation():
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except:
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self.add_wmask("0"*self.num_wmasks, port)
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def add_noop_clock_one_port(self, port):
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""" Add the control values for a noop to a single port. Increments the period. """
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debug.info(2, 'Clock only on port {}'.format(port))
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self.fn_cycle_comments.append('Clock only on port {}'.format(port))
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self.append_cycle_comment(port, 'Clock only on port {}'.format(port))
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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self.add_noop_one_port(port)
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#Add noops to all other ports.
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for unselected_port in self.all_ports:
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if unselected_port != port:
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self.add_noop_one_port(unselected_port)
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def append_cycle_comment(self, port, comment):
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"""Add comment to list to be printed in stimulus file"""
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#Clean up time before appending. Make spacing dynamic as well.
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@ -19,7 +19,7 @@ import re
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import copy
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import importlib
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VERSION = "1.1.4"
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VERSION = "1.1.5"
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NAME = "OpenRAM v{}".format(VERSION)
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USAGE = "openram.py [options] <config file>\nUse -h for help.\n"
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