mirror of https://github.com/VLSIDA/OpenRAM.git
PEP8 cleanup
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43fe1ae023
commit
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@ -9,9 +9,10 @@ import debug
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from drc_value import *
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from drc_lut import *
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class design_rules(dict):
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"""
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This is a class that implements the design rules structures.
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"""
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This is a class that implements the design rules structures.
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"""
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def __init__(self, name):
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self.tech_name = name
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@ -7,9 +7,10 @@
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#
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import debug
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class drc_lut():
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"""
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Implement a lookup table of rules.
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"""
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Implement a lookup table of rules.
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Each element is a tuple with the last value being the rule.
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It searches through backwards until all of the key values are
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met and returns the rule value.
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@ -31,7 +32,6 @@ class drc_lut():
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for table_key in sorted(self.table.keys(), reverse=True):
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if self.match(key, table_key):
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return self.table[table_key]
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def match(self, key1, key2):
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"""
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@ -39,8 +39,8 @@ class drc_lut():
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(i.e. return false if key1<key2 for any pair.)
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"""
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# If any one pair is less than, return False
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debug.check(len(key1)==len(key2),"Comparing invalid key lengths.")
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for k1,k2 in zip(key1,key2):
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debug.check(len(key1) == len(key2), "Comparing invalid key lengths.")
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for k1, k2 in zip(key1, key2):
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if k1 < k2:
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return False
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return True
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@ -6,8 +6,9 @@
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# All rights reserved.
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#
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class drc_value():
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"""
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"""
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A single DRC value.
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"""
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def __init__(self, value):
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