mirror of https://github.com/VLSIDA/OpenRAM.git
Merge branch 'tech_migration' into dev
This commit is contained in:
mrg
commit
90fdaf902c
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@ -974,6 +974,7 @@ class layout():
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def create_channel_route(self, netlist,
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offset,
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layer_stack,
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layer_dirs=None,
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vertical=False):
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"""
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The net list is a list of the nets. Each net is a list of pins
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@ -1012,25 +1013,38 @@ class layout():
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def vcg_pin_overlap(pin1, pin2, vertical, pitch):
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""" Check for vertical or horizontal overlap of the two pins """
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# FIXME: If the pins are not in a row, this may break.
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# However, a top pin shouldn't overlap another top pin,
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# for example, so the
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# extra comparison *shouldn't* matter.
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# Pin 1 must be in the "BOTTOM" set
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x_overlap = pin1.by() < pin2.by() and abs(pin1.center().x-pin2.center().x)<pitch
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x_overlap = pin1.by() < pin2.by() and abs(pin1.center().x - pin2.center().x) < pitch
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# Pin 1 must be in the "LEFT" set
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y_overlap = pin1.lx() < pin2.lx() and abs(pin1.center().y-pin2.center().y)<pitch
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y_overlap = pin1.lx() < pin2.lx() and abs(pin1.center().y - pin2.center().y) < pitch
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overlaps = (not vertical and x_overlap) or (vertical and y_overlap)
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return overlaps
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if self.get_preferred_direction(layer_stack[0]) == "V":
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self.vertical_layer = layer_stack[0]
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self.horizontal_layer = layer_stack[2]
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if not layer_dirs:
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# Use the preferred layer directions
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if self.get_preferred_direction(layer_stack[0]) == "V":
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self.vertical_layer = layer_stack[0]
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self.horizontal_layer = layer_stack[2]
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else:
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self.vertical_layer = layer_stack[2]
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self.horizontal_layer = layer_stack[0]
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else:
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self.vertical_layer = layer_stack[2]
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self.horizontal_layer = layer_stack[0]
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# Use the layer directions specified to the router rather than
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# the preferred directions
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debug.check(layer_dirs[0] != layer_dirs[1], "Must have unique layer directions.")
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if layer_dirs[0] == "V":
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self.vertical_layer = layer_stack[0]
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self.horizontal_layer = layer_stack[2]
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else:
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self.horizontal_layer = layer_stack[0]
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self.vertical_layer = layer_stack[2]
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layer_stuff = self.get_layer_pitch(self.vertical_layer)
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(self.vertical_pitch, self.vertical_width, self.vertical_space) = layer_stuff
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@ -1113,17 +1127,17 @@ class layout():
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self.horizontal_pitch)
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offset += vector(0, self.horizontal_pitch)
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def create_vertical_channel_route(self, netlist, offset, layer_stack):
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def create_vertical_channel_route(self, netlist, offset, layer_stack, layer_dirs=None):
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"""
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Wrapper to create a vertical channel route
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"""
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self.create_channel_route(netlist, offset, layer_stack, vertical=True)
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self.create_channel_route(netlist, offset, layer_stack, layer_dirs, vertical=True)
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def create_horizontal_channel_route(self, netlist, offset, layer_stack):
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def create_horizontal_channel_route(self, netlist, offset, layer_stack, layer_dirs=None):
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"""
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Wrapper to create a horizontal channel route
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"""
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self.create_channel_route(netlist, offset, layer_stack, vertical=False)
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self.create_channel_route(netlist, offset, layer_stack, layer_dirs, vertical=False)
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def add_boundary(self, ll=vector(0, 0), ur=None):
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""" Add boundary for debugging dimensions """
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@ -28,7 +28,6 @@ class bitcell_array(bitcell_base_array):
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# the replica bitcell in the control logic
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# self.offset_all_coordinates()
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def create_netlist(self):
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""" Create and connect the netlist """
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self.add_modules()
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@ -56,22 +55,21 @@ class bitcell_array(bitcell_base_array):
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for col in range(self.column_size):
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for row in range(self.row_size):
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name = "bit_r{0}_c{1}".format(row, col)
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self.cell_inst[row,col]=self.add_inst(name=name,
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mod=self.cell)
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self.cell_inst[row, col]=self.add_inst(name=name,
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mod=self.cell)
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self.connect_inst(self.get_bitcell_pins(col, row))
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def analytical_power(self, corner, load):
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"""Power of Bitcell array and bitline in nW."""
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from tech import drc, parameter
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# Dynamic Power from Bitline
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bl_wire = self.gen_bl_wire()
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cell_load = 2 * bl_wire.return_input_cap()
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cell_load = 2 * bl_wire.return_input_cap()
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bl_swing = OPTS.rbl_delay_percentage
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freq = spice["default_event_frequency"]
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bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing)
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# Calculate the bitcell power which currently only includes leakage
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# Calculate the bitcell power which currently only includes leakage
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cell_power = self.cell.analytical_power(corner, load)
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# Leakage power grows with entire array and bitlines.
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@ -85,7 +83,7 @@ class bitcell_array(bitcell_base_array):
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else:
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width = self.width
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wl_wire = self.generate_rc_net(int(self.column_size), width, drc("minwidth_m1"))
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wl_wire.wire_c = 2*spice["min_tx_gate_c"] + wl_wire.wire_c # 2 access tx gate per cell
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wl_wire.wire_c = 2 * spice["min_tx_gate_c"] + wl_wire.wire_c # 2 access tx gate per cell
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return wl_wire
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def gen_bl_wire(self):
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@ -94,26 +92,26 @@ class bitcell_array(bitcell_base_array):
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else:
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height = self.height
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bl_pos = 0
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bl_wire = self.generate_rc_net(int(self.row_size-bl_pos), height, drc("minwidth_m1"))
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bl_wire = self.generate_rc_net(int(self.row_size - bl_pos), height, drc("minwidth_m1"))
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bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
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return bl_wire
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def get_wordline_cin(self):
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"""Get the relative input capacitance from the wordline connections in all the bitcell"""
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#A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns
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# A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns
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bitcell_wl_cin = self.cell.get_wl_cin()
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total_cin = bitcell_wl_cin * self.column_size
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return total_cin
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def graph_exclude_bits(self, targ_row, targ_col):
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"""Excludes bits in column from being added to graph except target"""
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#Function is not robust with column mux configurations
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# Function is not robust with column mux configurations
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for row in range(self.row_size):
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for col in range(self.column_size):
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if row == targ_row and col == targ_col:
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continue
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self.graph_inst_exclude.add(self.cell_inst[row,col])
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self.graph_inst_exclude.add(self.cell_inst[row, col])
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def get_cell_name(self, inst_name, row, col):
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"""Gets the spice name of the target bitcell."""
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return inst_name+'.x'+self.cell_inst[row,col].name, self.cell_inst[row,col]
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"""Gets the spice name of the target bitcell."""
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return inst_name + '.x' + self.cell_inst[row, col].name, self.cell_inst[row, col]
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@ -699,8 +699,13 @@ class port_data(design.design):
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bottom_names = self._get_bitline_pins(bot_inst_group, bit)
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top_names = self._get_bitline_pins(top_inst_group, bit)
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if bottom_names[0].layer == "m2":
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bitline_dirs = ("H", "V")
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elif bottom_names[0].layer == "m1":
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bitline_dirs = ("V", "H")
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route_map = list(zip(bottom_names, top_names))
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self.create_horizontal_channel_route(route_map, offset, self.m1_stack)
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self.create_horizontal_channel_route(route_map, offset, self.m1_stack, bitline_dirs)
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def connect_bitlines(self, inst1, inst2, num_bits,
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inst1_bls_template="{inst}_{bit}",
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@ -5,17 +5,14 @@
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from math import log
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import design
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import contact
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from tech import drc
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import debug
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import math
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from vector import vector
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from sram_factory import factory
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from globals import OPTS
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import logical_effort
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class single_level_column_mux_array(design.design):
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"""
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Dynamically generated column mux array.
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@ -56,7 +53,7 @@ class single_level_column_mux_array(design.design):
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self.add_routing()
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# Find the highest shapes to determine height before adding well
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highest = self.find_highest_coords()
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self.height = highest.y
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self.height = highest.y
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self.add_layout_pins()
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self.add_enclosure(self.mux_inst, "pwell")
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@ -74,22 +71,18 @@ class single_level_column_mux_array(design.design):
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self.add_pin("br_out_{}".format(i))
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self.add_pin("gnd")
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def add_modules(self):
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self.mux = factory.create(module_type="single_level_column_mux",
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bitcell_bl=self.bitcell_bl,
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bitcell_br=self.bitcell_br)
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self.add_mod(self.mux)
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def setup_layout_constants(self):
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self.column_addr_size = num_of_inputs = int(self.words_per_row / 2)
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self.column_addr_size = int(self.words_per_row / 2)
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self.width = self.columns * self.mux.width
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# one set of metal1 routes for select signals and a pair to interconnect the mux outputs bl/br
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# one extra route pitch is to space from the sense amp
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self.route_height = (self.words_per_row + 3)*self.m1_pitch
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self.route_height = (self.words_per_row + 3) * self.m1_pitch
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def create_array(self):
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self.mux_inst = []
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@ -101,8 +94,8 @@ class single_level_column_mux_array(design.design):
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self.connect_inst(["bl_{}".format(col_num),
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"br_{}".format(col_num),
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"bl_out_{}".format(int(col_num/self.words_per_row)),
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"br_out_{}".format(int(col_num/self.words_per_row)),
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"bl_out_{}".format(int(col_num / self.words_per_row)),
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"br_out_{}".format(int(col_num / self.words_per_row)),
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"sel_{}".format(col_num % self.words_per_row),
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"gnd"])
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@ -117,11 +110,9 @@ class single_level_column_mux_array(design.design):
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else:
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mirror = ""
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name = "XMUX{0}".format(col_num)
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offset = vector(xoffset, self.route_height)
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self.mux_inst[col_num].place(offset=offset, mirror=mirror)
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def add_layout_pins(self):
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""" Add the pins after we determine the height. """
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# For every column, add a pass gate
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@ -131,18 +122,17 @@ class single_level_column_mux_array(design.design):
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self.add_layout_pin(text="bl_{}".format(col_num),
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layer="m2",
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offset=offset,
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height=self.height-offset.y)
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height=self.height - offset.y)
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offset = mux_inst.get_pin("br").ll()
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self.add_layout_pin(text="br_{}".format(col_num),
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layer="m2",
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offset=offset,
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height=self.height-offset.y)
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height=self.height - offset.y)
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for inst in self.mux_inst:
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self.copy_layout_pin(inst, "gnd")
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def add_routing(self):
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self.add_horizontal_input_rail()
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self.add_vertical_poly_rail()
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@ -151,7 +141,7 @@ class single_level_column_mux_array(design.design):
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def add_horizontal_input_rail(self):
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""" Create address input rails on M1 below the mux transistors """
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for j in range(self.words_per_row):
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offset = vector(0, self.route_height + (j-self.words_per_row)*self.m1_pitch)
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offset = vector(0, self.route_height + (j - self.words_per_row) * self.m1_pitch)
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self.add_layout_pin(text="sel_{}".format(j),
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layer="m1",
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offset=offset,
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@ -167,9 +157,10 @@ class single_level_column_mux_array(design.design):
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# Add the column x offset to find the right select bit
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gate_offset = self.mux_inst[col].get_pin("sel").bc()
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# height to connect the gate to the correct horizontal row
|
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sel_height = self.get_pin("sel_{}".format(sel_index)).by()
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# sel_height = self.get_pin("sel_{}".format(sel_index)).by()
|
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# use the y offset from the sel pin and the x offset from the gate
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offset = vector(gate_offset.x,self.get_pin("sel_{}".format(sel_index)).cy())
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offset = vector(gate_offset.x,
|
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self.get_pin("sel_{}".format(sel_index)).cy())
|
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# Add the poly contact with a shift to account for the rotation
|
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self.add_via_center(layers=("m1", "contact", "poly"),
|
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offset=offset)
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@ -182,11 +173,11 @@ class single_level_column_mux_array(design.design):
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bl_offset = self.mux_inst[j].get_pin("bl_out").bc()
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br_offset = self.mux_inst[j].get_pin("br_out").bc()
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|
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bl_out_offset = bl_offset - vector(0,(self.words_per_row+1)*self.m1_pitch)
|
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br_out_offset = br_offset - vector(0,(self.words_per_row+2)*self.m1_pitch)
|
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bl_out_offset = bl_offset - vector(0, (self.words_per_row + 1) * self.m1_pitch)
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br_out_offset = br_offset - vector(0, (self.words_per_row + 2) * self.m1_pitch)
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bl_out_offset_end = bl_out_offset + vector(0,self.route_height)
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br_out_offset_end = br_out_offset + vector(0,self.route_height)
|
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bl_out_offset_end = bl_out_offset + vector(0, self.route_height)
|
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br_out_offset_end = br_out_offset + vector(0, self.route_height)
|
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|
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if cell_properties.bitcell.mirror.y and j % 2:
|
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tmp_bl_out_end = br_out_offset_end
|
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|
|
@ -208,21 +199,20 @@ class single_level_column_mux_array(design.design):
|
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else:
|
||||
dist = 0
|
||||
|
||||
self.add_path("m1", [bl_out_offset, bl_out_offset+vector(width+dist,0)])
|
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self.add_path("m1", [br_out_offset, br_out_offset+vector(width-dist,0)])
|
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self.add_path("m1", [bl_out_offset, bl_out_offset + vector(width + dist, 0)])
|
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self.add_path("m1", [br_out_offset, br_out_offset + vector(width - dist, 0)])
|
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|
||||
# Extend the bitline output rails and gnd downward on the first bit of each n-way mux
|
||||
self.add_layout_pin_segment_center(text="bl_out_{}".format(int(j/self.words_per_row)),
|
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self.add_layout_pin_segment_center(text="bl_out_{}".format(int(j / self.words_per_row)),
|
||||
layer="m2",
|
||||
start=bl_out_offset,
|
||||
end=tmp_bl_out_end)
|
||||
self.add_layout_pin_segment_center(text="br_out_{}".format(int(j/self.words_per_row)),
|
||||
self.add_layout_pin_segment_center(text="br_out_{}".format(int(j / self.words_per_row)),
|
||||
layer="m2",
|
||||
start=br_out_offset,
|
||||
end=tmp_br_out_end)
|
||||
|
||||
|
||||
# This via is on the right of the wire
|
||||
# This via is on the right of the wire
|
||||
self.add_via_center(layers=self.m1_stack,
|
||||
offset=bl_out_offset)
|
||||
|
||||
|
|
@ -231,20 +221,19 @@ class single_level_column_mux_array(design.design):
|
|||
offset=br_out_offset)
|
||||
|
||||
else:
|
||||
|
||||
self.add_path("m2", [ bl_out_offset, tmp_bl_out_end])
|
||||
self.add_path("m2", [ br_out_offset, tmp_br_out_end])
|
||||
self.add_path("m2", [bl_out_offset, tmp_bl_out_end])
|
||||
self.add_path("m2", [br_out_offset, tmp_br_out_end])
|
||||
|
||||
# This via is on the right of the wire
|
||||
self.add_via_center(layers=self.m1_stack,
|
||||
offset=bl_out_offset)
|
||||
# This via is on the left of the wire
|
||||
# This via is on the left of the wire
|
||||
self.add_via_center(layers=self.m1_stack,
|
||||
offset=br_out_offset)
|
||||
|
||||
def get_drain_cin(self):
|
||||
"""Get the relative capacitance of the drain of the NMOS pass TX"""
|
||||
from tech import parameter
|
||||
#Bitcell drain load being used to estimate mux NMOS drain load
|
||||
# Bitcell drain load being used to estimate mux NMOS drain load
|
||||
drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap'])
|
||||
return drain_load
|
||||
return drain_load
|
||||
|
|
|
|||
|
|
@ -0,0 +1,49 @@
|
|||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
from sram_factory import factory
|
||||
import debug
|
||||
|
||||
#@unittest.skip("SKIPPING 04_driver_test")
|
||||
|
||||
class single_level_column_mux_pbitcell_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
|
||||
globals.init_openram(config_file)
|
||||
|
||||
# check single level column mux in multi-port
|
||||
OPTS.bitcell = "pbitcell"
|
||||
OPTS.num_rw_ports = 1
|
||||
OPTS.num_r_ports = 1
|
||||
OPTS.num_w_ports = 1
|
||||
|
||||
factory.reset()
|
||||
debug.info(2, "Checking column mux for pbitcell (innermost connections)")
|
||||
tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0")
|
||||
self.local_check(tx)
|
||||
|
||||
factory.reset()
|
||||
debug.info(2, "Checking column mux for pbitcell (outermost connections)")
|
||||
tx = factory.create(module_type="single_level_column_mux",tx_size=8, bitcell_bl="bl2", bitcell_br="br2")
|
||||
self.local_check(tx)
|
||||
|
||||
globals.end_openram()
|
||||
|
||||
# run the test from the command line
|
||||
if __name__ == "__main__":
|
||||
(OPTS, args) = globals.parse_args()
|
||||
del sys.argv[1:]
|
||||
header(__file__, OPTS.tech_name)
|
||||
unittest.main(testRunner=debugTestRunner())
|
||||
|
|
@ -28,22 +28,6 @@ class single_level_column_mux_test(openram_test):
|
|||
tx = factory.create(module_type="single_level_column_mux", tx_size=8)
|
||||
self.local_check(tx)
|
||||
|
||||
# check single level column mux in multi-port
|
||||
OPTS.bitcell = "pbitcell"
|
||||
OPTS.num_rw_ports = 1
|
||||
OPTS.num_r_ports = 1
|
||||
OPTS.num_w_ports = 1
|
||||
|
||||
factory.reset()
|
||||
debug.info(2, "Checking column mux for pbitcell (innermost connections)")
|
||||
tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0")
|
||||
self.local_check(tx)
|
||||
|
||||
factory.reset()
|
||||
debug.info(2, "Checking column mux for pbitcell (outermost connections)")
|
||||
tx = factory.create(module_type="single_level_column_mux",tx_size=8, bitcell_bl="bl2", bitcell_br="br2")
|
||||
self.local_check(tx)
|
||||
|
||||
globals.end_openram()
|
||||
|
||||
# run the test from the command line
|
||||
|
|
|
|||
|
|
@ -0,0 +1,78 @@
|
|||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2019 Regents of the University of California
|
||||
# All rights reserved.
|
||||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
from sram_factory import factory
|
||||
import debug
|
||||
|
||||
class port_data_1rw_1r_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
|
||||
globals.init_openram(config_file)
|
||||
from sram_config import sram_config
|
||||
|
||||
OPTS.bitcell = "bitcell_1w_1r"
|
||||
OPTS.num_rw_ports = 0
|
||||
OPTS.num_r_ports = 1
|
||||
OPTS.num_w_ports = 1
|
||||
|
||||
c = sram_config(word_size=4,
|
||||
num_words=16)
|
||||
|
||||
c.words_per_row=1
|
||||
factory.reset()
|
||||
c.recompute_sizes()
|
||||
debug.info(1, "No column mux")
|
||||
a = factory.create("port_data", sram_config=c, port=0)
|
||||
self.local_check(a)
|
||||
a = factory.create("port_data", sram_config=c, port=1)
|
||||
self.local_check(a)
|
||||
|
||||
c.num_words=32
|
||||
c.words_per_row=2
|
||||
factory.reset()
|
||||
c.recompute_sizes()
|
||||
debug.info(1, "Two way column mux")
|
||||
a = factory.create("port_data", sram_config=c, port=0)
|
||||
self.local_check(a)
|
||||
a = factory.create("port_data", sram_config=c, port=1)
|
||||
self.local_check(a)
|
||||
|
||||
c.num_words=64
|
||||
c.words_per_row=4
|
||||
factory.reset()
|
||||
c.recompute_sizes()
|
||||
debug.info(1, "Four way column mux")
|
||||
a = factory.create("port_data", sram_config=c, port=0)
|
||||
self.local_check(a)
|
||||
a = factory.create("port_data", sram_config=c, port=1)
|
||||
self.local_check(a)
|
||||
|
||||
c.word_size=2
|
||||
c.num_words=128
|
||||
c.words_per_row=8
|
||||
factory.reset()
|
||||
c.recompute_sizes()
|
||||
debug.info(1, "Eight way column mux")
|
||||
a = factory.create("port_data", sram_config=c, port=0)
|
||||
self.local_check(a)
|
||||
a = factory.create("port_data", sram_config=c, port=1)
|
||||
self.local_check(a)
|
||||
|
||||
globals.end_openram()
|
||||
|
||||
# run the test from the command line
|
||||
if __name__ == "__main__":
|
||||
(OPTS, args) = globals.parse_args()
|
||||
del sys.argv[1:]
|
||||
header(__file__, OPTS.tech_name)
|
||||
unittest.main(testRunner=debugTestRunner())
|
||||
|
|
@ -55,52 +55,6 @@ class port_data_test(openram_test):
|
|||
a = factory.create("port_data", sram_config=c, port=0)
|
||||
self.local_check(a)
|
||||
|
||||
OPTS.bitcell = "bitcell_1w_1r"
|
||||
OPTS.num_rw_ports = 0
|
||||
OPTS.num_r_ports = 1
|
||||
OPTS.num_w_ports = 1
|
||||
|
||||
c.num_words=16
|
||||
c.words_per_row=1
|
||||
factory.reset()
|
||||
c.recompute_sizes()
|
||||
debug.info(1, "No column mux")
|
||||
a = factory.create("port_data", sram_config=c, port=0)
|
||||
self.local_check(a)
|
||||
a = factory.create("port_data", sram_config=c, port=1)
|
||||
self.local_check(a)
|
||||
|
||||
c.num_words=32
|
||||
c.words_per_row=2
|
||||
factory.reset()
|
||||
c.recompute_sizes()
|
||||
debug.info(1, "Two way column mux")
|
||||
a = factory.create("port_data", sram_config=c, port=0)
|
||||
self.local_check(a)
|
||||
a = factory.create("port_data", sram_config=c, port=1)
|
||||
self.local_check(a)
|
||||
|
||||
c.num_words=64
|
||||
c.words_per_row=4
|
||||
factory.reset()
|
||||
c.recompute_sizes()
|
||||
debug.info(1, "Four way column mux")
|
||||
a = factory.create("port_data", sram_config=c, port=0)
|
||||
self.local_check(a)
|
||||
a = factory.create("port_data", sram_config=c, port=1)
|
||||
self.local_check(a)
|
||||
|
||||
c.word_size=2
|
||||
c.num_words=128
|
||||
c.words_per_row=8
|
||||
factory.reset()
|
||||
c.recompute_sizes()
|
||||
debug.info(1, "Eight way column mux")
|
||||
a = factory.create("port_data", sram_config=c, port=0)
|
||||
self.local_check(a)
|
||||
a = factory.create("port_data", sram_config=c, port=1)
|
||||
self.local_check(a)
|
||||
|
||||
globals.end_openram()
|
||||
|
||||
# run the test from the command line
|
||||
|
|
|
|||
Loading…
Reference in New Issue