mirror of https://github.com/VLSIDA/OpenRAM.git
Fix voltage_map names (these do not need to match pg_pin names)
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@ -243,8 +243,8 @@ class lib:
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self.lib.write(" default_max_fanout : 4.0 ;\n")
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self.lib.write(" default_connection_class : universal ;\n\n")
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self.lib.write(" voltage_map ( vdd, {} );\n".format(tech.spice["nom_supply_voltage"]))
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self.lib.write(" voltage_map ( gnd, 0 );\n\n")
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self.lib.write(" voltage_map ( VDD, {} );\n".format(tech.spice["nom_supply_voltage"]))
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self.lib.write(" voltage_map ( GND, 0 );\n\n")
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def create_list(self,values):
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""" Helper function to create quoted, line wrapped list """
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