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OpenRAM
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248 Commits

Author SHA1 Message Date
Joey Kunzler ee1de9ac8c Merge branch 's8_update' of github.com:VLSIDA/PrivateRAM into s8_update 2020-04-20 22:14:09 -07:00
Joey Kunzler 829f3e03fa col_mux.py update with correct contacts 2020-04-20 22:08:29 -07:00
Joey Kunzler 63bea67fb5 col_mux.py changes 2020-04-20 20:22:46 -07:00
jcirimel f590ecf83c fix minimum pinv sizing 2020-04-18 05:51:21 -07:00
jcirimel add9ec7b28 remove excess newlines 2020-04-18 05:42:23 -07:00
jcirimel 85bc801689 fix pinv drc bug 2020-04-18 05:34:55 -07:00
jcirimel 1f094b03bc use more optimal discrete pinv sizing 2020-04-18 05:26:39 -07:00
jcirimel 486819ae0d fix width bin typo 2020-04-17 15:27:36 -07:00
jcirimel a158ad1e81 add missing import 2020-04-17 14:24:52 -07:00
jcirimel 24e0e326d4 merge dev in to disc... 2020-04-16 02:18:39 -07:00
jcirimel ebb1a7bedb merge local with dev 2020-04-16 02:16:56 -07:00
jcirimel 6c1c72c520 fix pgates binning off-by-one 2020-04-15 04:09:58 -07:00
mrg 43dcf675a1 Move pnand outputs to M1. Debug hierarchical decoder multirow. 2020-04-14 10:52:25 -07:00
jcirimel 5f4ed47c57 netlist only discrete simulating 2020-04-13 20:48:34 -07:00
jcirimel afcb5174ac discrete dff tests working 2020-04-11 01:19:04 -07:00
mrg 2e67d44cd7 First pass of multiple bitcells per decoder row 2020-04-10 13:29:41 -07:00
jcirimel a0eb9839ad revert units on sp_lib, begin discrete tx simulation 2020-04-09 19:39:21 -07:00
mrg 745450fadc Syntax error 2020-04-08 17:04:50 -07:00
mrg cddfaa0dc8 Tech dependent fudge factor 2020-04-08 17:04:14 -07:00
mrg 0c27942bb2 Dynamically try and DRC decoder for height 2020-04-08 16:45:28 -07:00
Hunter Nichols 4103745de2 Merged with dev, fixed conflict in ptx 2020-04-08 02:33:05 -07:00
Hunter Nichols 95363856e4 Added logical effort and input load for ptx module. 2020-04-08 02:29:57 -07:00
mrg a3797094d0 Swap lvs and sp dimensions for s8 2020-04-07 10:37:49 -07:00
mrg ab5dd47182 Ptx is in microns if lvs_lib exists 2020-04-03 14:06:56 -07:00
mrg 0d6c84036d Adjust fudge factor for pin spacing. 2020-04-02 09:47:13 -07:00
mrg 3b662026d2 pnand3 constant hack for input separation 2020-04-01 11:36:04 -07:00
mrg 7956b63d9f Add licon option to precharge 2020-04-01 11:26:45 -07:00
mrg 3074cf3b86 Small format cleanup 2020-04-01 11:15:29 -07:00
mrg bc9cbe70a7 Poly overlap doesn't convert to tx device 2020-04-01 09:42:07 -07:00
mrg d2c97d75a7 Add well contact and min area to power pin of precharge 2020-03-26 11:49:32 -07:00
mrg 1e3734cb26 Hack to fix pnand3 in freepdk45 2020-03-26 11:08:53 -07:00
mrg 2f353187ba Skywater extraction mode for si unit scales 2020-03-24 12:41:15 -07:00
mrg 1e2163c3a6 Hack for pnand3 pin spacing 2020-03-24 12:40:41 -07:00
mrg e9d0db44fd Add li_stack contact to ptx and pgate if it exists. 2020-03-23 16:55:38 -07:00
mrg f491876a5a Move up B input in pnor2 2020-03-23 13:49:08 -07:00
mrg f598a359d5 Remove unused contact in pnor2 2020-03-23 11:55:17 -07:00
mrg 717cbb0fe5 Remove unused contact in pnand3 2020-03-23 11:52:19 -07:00
mrg 0ee6963198 Remove unused contact in pnand2 2020-03-23 11:46:21 -07:00
mrg f21791a904 Add source drain contact options to ptx. 2020-03-23 11:36:45 -07:00
mrg c5a1be703c Rotate via and PEP8 formatting 2020-03-06 13:39:46 -08:00
mrg 23501c7b35 Convert pnand+pinv to pand in decoders. 2020-03-06 13:26:40 -08:00
mrg 5312629702 Remove jog in precharge. Jog is in port data 2020-03-05 12:10:13 -08:00
mrg 287a31f598 Precharge updates. 
Enable different layers for bitlines.
Jog bitlines to fit precharge transistors for close proximity bitlines.
PEP8 cleanup.
 2020-03-04 17:39:11 -08:00
mrg 7ba9e09e12 Incomplete precharge layer decoupling 2020-03-04 22:23:05 +00:00
mrg bb2305d56a PEP8 format fixes 2020-02-28 18:24:39 +00:00
mrg 0b73979388 Space inputs by M1 pitch 2020-02-28 18:23:49 +00:00
mrg 073bd47b31 Add source/drain/gate to structure 2020-02-28 18:23:36 +00:00
mrg 266d68c395 Generalize pgate width based on nwell/pwell contacts 2020-02-25 17:09:07 +00:00
mrg 254e584e35 Cleanup and simplify ptx for multiple technologies 2020-02-25 00:36:22 +00:00
mrg 585a708e0c Generalize y offsets in pnand3 2020-02-25 00:36:02 +00:00