OpenRAM/compiler/pgates
mrg f491876a5a Move up B input in pnor2 2020-03-23 13:49:08 -07:00
..
pand2.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
pand3.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
pbuf.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
pdriver.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
pgate.py Incomplete precharge layer decoupling 2020-03-04 22:23:05 +00:00
pinv.py Generalize pgate width based on nwell/pwell contacts 2020-02-25 17:09:07 +00:00
pinvbuf.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
pnand2.py Remove unused contact in pnand2 2020-03-23 11:46:21 -07:00
pnand3.py Remove unused contact in pnand3 2020-03-23 11:52:19 -07:00
pnor2.py Move up B input in pnor2 2020-03-23 13:49:08 -07:00
precharge.py Remove jog in precharge. Jog is in port data 2020-03-05 12:10:13 -08:00
ptristate_inv.py Cleanup and rename vias. 2020-01-30 01:45:33 +00:00
ptx.py Add source drain contact options to ptx. 2020-03-23 11:36:45 -07:00
pwrite_driver.py Nwell fixes in pgates. 2020-02-06 16:20:09 +00:00
single_level_column_mux.py port_data: Each submodule now specifies their bl/br names 2020-02-12 15:00:50 +01:00