OpenRAM/compiler/pgates
jcirimel ebb1a7bedb merge local with dev 2020-04-16 02:16:56 -07:00
..
pand2.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
pand3.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
pbuf.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
pdriver.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
pgate.py revert units on sp_lib, begin discrete tx simulation 2020-04-09 19:39:21 -07:00
pinv.py merge local with dev 2020-04-16 02:16:56 -07:00
pinvbuf.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
pnand2.py Move pnand outputs to M1. Debug hierarchical decoder multirow. 2020-04-14 10:52:25 -07:00
pnand3.py Move pnand outputs to M1. Debug hierarchical decoder multirow. 2020-04-14 10:52:25 -07:00
pnor2.py Move up B input in pnor2 2020-03-23 13:49:08 -07:00
precharge.py revert units on sp_lib, begin discrete tx simulation 2020-04-09 19:39:21 -07:00
ptristate_inv.py Cleanup and rename vias. 2020-01-30 01:45:33 +00:00
ptx.py Move pnand outputs to M1. Debug hierarchical decoder multirow. 2020-04-14 10:52:25 -07:00
pwrite_driver.py Nwell fixes in pgates. 2020-02-06 16:20:09 +00:00
single_level_column_mux.py port_data: Each submodule now specifies their bl/br names 2020-02-12 15:00:50 +01:00