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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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f21791a904ee2ca16fb0e5db4f4a6a4757d4d874
OpenRAM/compiler/pgates
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mrg f21791a904 Add source drain contact options to ptx.
2020-03-23 11:36:45 -07:00
..
pand2.py
Clean up and generalize layer rules.
2019-12-17 11:03:36 -08:00
pand3.py
Clean up and generalize layer rules.
2019-12-17 11:03:36 -08:00
pbuf.py
Clean up and generalize layer rules.
2019-12-17 11:03:36 -08:00
pdriver.py
Clean up and generalize layer rules.
2019-12-17 11:03:36 -08:00
pgate.py
Incomplete precharge layer decoupling
2020-03-04 22:23:05 +00:00
pinv.py
Generalize pgate width based on nwell/pwell contacts
2020-02-25 17:09:07 +00:00
pinvbuf.py
Clean up and generalize layer rules.
2019-12-17 11:03:36 -08:00
pnand2.py
Rotate via and PEP8 formatting
2020-03-06 13:39:46 -08:00
pnand3.py
Rotate via and PEP8 formatting
2020-03-06 13:39:46 -08:00
pnor2.py
Add source drain contact options to ptx.
2020-03-23 11:36:45 -07:00
precharge.py
Remove jog in precharge. Jog is in port data
2020-03-05 12:10:13 -08:00
ptristate_inv.py
Cleanup and rename vias.
2020-01-30 01:45:33 +00:00
ptx.py
Add source drain contact options to ptx.
2020-03-23 11:36:45 -07:00
pwrite_driver.py
Nwell fixes in pgates.
2020-02-06 16:20:09 +00:00
single_level_column_mux.py
port_data: Each submodule now specifies their bl/br names
2020-02-12 15:00:50 +01:00
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