mrg 073bd47b31 Add source/drain/gate to structure		2020-02-28 18:23:36 +00:00
..
pand2.py	Clean up and generalize layer rules.	2019-12-17 11:03:36 -08:00
pand3.py	Clean up and generalize layer rules.	2019-12-17 11:03:36 -08:00
pbuf.py	Clean up and generalize layer rules.	2019-12-17 11:03:36 -08:00
pdriver.py	Clean up and generalize layer rules.	2019-12-17 11:03:36 -08:00
pgate.py	Generalize pgate width based on nwell/pwell contacts	2020-02-25 17:09:07 +00:00
pinv.py	Generalize pgate width based on nwell/pwell contacts	2020-02-25 17:09:07 +00:00
pinvbuf.py	Clean up and generalize layer rules.	2019-12-17 11:03:36 -08:00
pnand2.py	Generalize pgate width based on nwell/pwell contacts	2020-02-25 17:09:07 +00:00
pnand3.py	Generalize pgate width based on nwell/pwell contacts	2020-02-25 17:09:07 +00:00
pnor2.py	Generalize pgate width based on nwell/pwell contacts	2020-02-25 17:09:07 +00:00
precharge.py	bank: Connect instances by their individual bl/br names	2020-02-12 15:00:50 +01:00
ptristate_inv.py	Cleanup and rename vias.	2020-01-30 01:45:33 +00:00
ptx.py	Add source/drain/gate to structure	2020-02-28 18:23:36 +00:00
pwrite_driver.py	Nwell fixes in pgates.	2020-02-06 16:20:09 +00:00
single_level_column_mux.py	port_data: Each submodule now specifies their bl/br names	2020-02-12 15:00:50 +01:00