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OpenRAM
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2076 Commits

Author SHA1 Message Date
Joey Kunzler ee1de9ac8c Merge branch 's8_update' of github.com:VLSIDA/PrivateRAM into s8_update 2020-04-20 22:14:09 -07:00
Joey Kunzler 829f3e03fa col_mux.py update with correct contacts 2020-04-20 22:08:29 -07:00
Joey Kunzler 63bea67fb5 col_mux.py changes 2020-04-20 20:22:46 -07:00
mrg 2a9dde5401 Merge branch 'tech_migration' into dev 2020-04-20 09:07:36 -07:00
jcirimel 32317ce3a5 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev 2020-04-18 14:23:31 -07:00
jcirimel f590ecf83c fix minimum pinv sizing 2020-04-18 05:51:21 -07:00
jcirimel add9ec7b28 remove excess newlines 2020-04-18 05:42:23 -07:00
jcirimel 85bc801689 fix pinv drc bug 2020-04-18 05:34:55 -07:00
jcirimel 1f094b03bc use more optimal discrete pinv sizing 2020-04-18 05:26:39 -07:00
jcirimel 486819ae0d fix width bin typo 2020-04-17 15:27:36 -07:00
jcirimel a158ad1e81 add missing import 2020-04-17 14:24:52 -07:00
mrg cbb67ad483 Update to run LVS when no DRC errors too. 2020-04-17 13:57:52 -07:00
Joey Kunzler 7920b0cef9 m3 min area rounding fix 2020-04-17 12:36:48 -07:00
Joey Kunzler fbc6dfdaac split pbitcell tests 2020-04-17 12:26:18 -07:00
mrg f1925420cf Only allow DRC fail with LVS pass if using Magic. 2020-04-17 10:30:26 -07:00
mrg 75fce9894c Allow LVS to run even if DRC fails. 2020-04-17 09:35:07 -07:00
jcirimel 9316fb8b01 Merge branch 'dev' into discrete_models 2020-04-16 16:48:21 -07:00
jcirimel ed54c7ab83 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev 2020-04-16 16:48:07 -07:00
mrg 8ece411954 Merge branch 'dev' into tech_migration 2020-04-16 11:32:02 -07:00
mrg 843e9414df Parameterize vdd and gnd pin in write driver array. 2020-04-16 11:28:35 -07:00
mrg 770533e7b1 Parameterize vdd and gnd pin in sense amp array. 2020-04-16 11:27:26 -07:00
mrg d1319d633d Don't widen too short wires either 2020-04-16 11:02:54 -07:00
jcirimel 24e0e326d4 merge dev in to disc... 2020-04-16 02:18:39 -07:00
jcirimel ebb1a7bedb merge local with dev 2020-04-16 02:16:56 -07:00
mrg b347e3f7a8 Try both layers for reversed layer stacks. 2020-04-15 16:49:04 -07:00
mrg 9d2902de9e Conditional well spacing 2020-04-15 15:55:49 -07:00
mrg 94eb2afa36 Change to callable DRC rule. Use bottom coordinate for bus offsets. 2020-04-15 15:29:55 -07:00
mrg e95c97d7a5 PEP8 cleanup 2020-04-15 14:29:43 -07:00
mrg 1564d6e02b PEP8 cleanup 2020-04-15 11:24:28 -07:00
mrg 43fe1ae023 Improve pitch computation 2020-04-15 11:16:45 -07:00
mrg 331a4f4606 Fix wire width bug in short jogs. PEP8 cleanup. 2020-04-15 09:48:42 -07:00
jcirimel 6c1c72c520 fix pgates binning off-by-one 2020-04-15 04:09:58 -07:00
mrg 0941ebc3da Fix well spacing issue 2020-04-14 14:08:07 -07:00
mrg 32d190b8b1 Jog connection on M1 for bank select. 2020-04-14 12:15:56 -07:00
mrg 43dcf675a1 Move pnand outputs to M1. Debug hierarchical decoder multirow. 2020-04-14 10:52:25 -07:00
jcirimel 5f4ed47c57 netlist only discrete simulating 2020-04-13 20:48:34 -07:00
jcirimel afcb5174ac discrete dff tests working 2020-04-11 01:19:04 -07:00
mrg 2e67d44cd7 First pass of multiple bitcells per decoder row 2020-04-10 13:29:41 -07:00
jcirimel a0eb9839ad revert units on sp_lib, begin discrete tx simulation 2020-04-09 19:39:21 -07:00
mrg 7888e54fc4 Remove dynamic bitcell multiple detection. 
Check for decoder bitcell multiple in tech file or assume 1.
PEP8 fixes.
 2020-04-09 11:38:18 -07:00
mrg 8a55c223df Use single height for netlist_only mode 2020-04-09 09:48:54 -07:00
mrg 58fbc5351a Change rows to outputs in hierarchical decoder 2020-04-08 17:05:16 -07:00
mrg 745450fadc Syntax error 2020-04-08 17:04:50 -07:00
mrg cddfaa0dc8 Tech dependent fudge factor 2020-04-08 17:04:14 -07:00
mrg ade3b78711 Add exception errors file 2020-04-08 16:55:45 -07:00
mrg 0c27942bb2 Dynamically try and DRC decoder for height 2020-04-08 16:45:28 -07:00
Hunter Nichols 4103745de2 Merged with dev, fixed conflict in ptx 2020-04-08 02:33:05 -07:00
Hunter Nichols 95363856e4 Added logical effort and input load for ptx module. 2020-04-08 02:29:57 -07:00
mrg 7872b6a68c Merge branch 'dev' into tech_migration 2020-04-07 10:42:05 -07:00
mrg a3797094d0 Swap lvs and sp dimensions for s8 2020-04-07 10:37:49 -07:00