mrg 75fce9894c Allow LVS to run even if DRC fails.

2020-04-17 09:35:07 -07:00

..

base

Don't widen too short wires either

2020-04-16 11:02:54 -07:00

bitcells

Small format cleanup

2020-04-01 11:15:29 -07:00

characterizer

Merge branch 'dev' into custom_mod

2020-04-03 17:05:56 -07:00

datasheet

Convert capital names to lower case for consistency

2019-08-21 13:45:34 -07:00

drc

PEP8 cleanup

2020-04-15 11:24:28 -07:00

example_configs

revert example scn4m to non netlist only

2020-02-09 23:52:11 -08:00

gdsMill

added purposes to addText(), removed reference to specific tech from gdsMill

2020-02-19 16:26:52 -08:00

modules

Parameterize vdd and gnd pin in write driver array.

2020-04-16 11:28:35 -07:00

pgates

Move pnand outputs to M1. Debug hierarchical decoder multirow.

2020-04-14 10:52:25 -07:00

router

tech: Make power_grid configurable

2020-01-28 12:06:34 +01:00

sram

Fix lvs_write in sram class

2020-04-06 15:20:59 -07:00

tests

Allow LVS to run even if DRC fails.

2020-04-17 09:35:07 -07:00

verify

Don't force check in lib characterization. PEP8 formatting.

2020-04-02 12:52:42 -07:00

debug.py

Add layer-purpose GDS support. Various PEP8 fixes.

2019-11-14 18:17:20 +00:00

gen_stimulus.py

Remove some flake8 errors/warnings.

2019-10-02 23:26:02 +00:00

globals.py

Remove dynamic bitcell multiple detection.

2020-04-09 11:38:18 -07:00

Makefile

…

openram.py

Only setup bitcell when running top-level OpenRAM

2019-11-26 13:54:37 -08:00

options.py

Blackbox option for DRC waivers

2019-11-29 15:50:32 -08:00

run_profile.sh

…

sram_factory.py

sram_factory: Add check for duplicate module name

2019-12-19 16:31:52 +01:00

view_profile.py

Remove some flake8 errors/warnings.

2019-10-02 23:26:02 +00:00