mrg
4d85640a00
Change col addr spacing to col addr size
2020-02-07 22:20:16 +00:00
mrg
2ff058f5d5
PEP8 Cleanup and reverse pitch offset of col addr routing
2020-02-06 22:59:30 +00:00
mrg
4b06ab9eaf
Move port 2 column address bus down.
...
PEP 8 cleanup.
2020-02-06 19:46:10 +00:00
Jesse Cirimelli-Low
b107934672
fix styling
2020-02-06 12:15:52 +00:00
Jesse Cirimelli-Low
3a06141030
add simple sram sizing for netlist only
2020-02-06 12:10:49 +00:00
mrg
79391b84da
Cleanup and rename vias.
2020-01-30 01:45:33 +00:00
Bastian Koppelmann
9749c522d1
tech: Make power_grid configurable
...
this is the first step to allow engineers, porting technologies, more room
for routing their handmade cells.
For now, we don't allow the specification of power_grids where the lower layer
prefers to be routed vertically. This is due to the router not
connecting some pins properly in that case.
Signed-off-by: Bastian Koppelmann <[email protected]
2020-01-28 12:06:34 +01:00
Jesse Cirimelli-Low
6e070925b6
update magic for multiport
2020-01-28 02:32:34 +00:00
Jesse Cirimelli-Low
30604fb093
add multiport support for pex labels
2020-01-28 00:28:55 +00:00
Jesse Cirimelli-Low
1a97dfc63e
syncronize bitline naming convention betwen bitcell and pbitcell
2020-01-27 11:50:43 +00:00
Jesse Cirimelli-Low
d42cd9a281
pbitcell working with bitline adjustments
2020-01-27 10:03:31 +00:00
Jesse Cirimelli-Low
1062cbfd7f
begin fixes to pbitcell, prepare multibank pex
2020-01-24 10:24:29 +00:00
jcirimel
40c01dab85
fix bl in stim file
2020-01-21 01:44:15 -08:00
jcirimel
73691f6054
fix bug in top level bitline label placement
2020-01-21 00:20:52 -08:00
Jesse Cirimelli-Low
5778901cfe
pull bitline labels to top level spice
2020-01-20 12:16:30 +00:00
jcirimel
364842569a
fix s_en in stim
2020-01-16 12:16:49 -08:00
jcirimel
075bf0d841
label bitcell in stim, add s_en top level to stim
2020-01-16 03:51:29 -08:00
Jesse Cirimelli-Low
3ab99d7f9c
update gds library, generalize geometry reverse transform function
2019-12-24 05:01:55 +00:00
Bastian Koppelmann
fab963701b
sram_base: Instantiate "dff_array" and "bank" through sram_factory
...
Signed-off-by: Bastian Koppelmann <[email protected]
2019-12-18 17:33:50 +01:00
Jesse Cirimelli-Low
88d3da0b4a
fix control logic pex labels with multiport
2019-12-18 12:45:12 +00:00
jcirimel
f0958b0b11
squashed update of pex progress due to timezone error
2019-12-18 03:03:13 -08:00
Matt Guthaus
ed28b4983b
Clean up and generalize layer rules.
...
Convert metalN to mN.
Generalize helper constants in modules for
space, width, enclose, etc.
Use layer stacks whever possible.
Try to remove drc() calls in liu of helper constants.
2019-12-17 11:03:36 -08:00
Matt Guthaus
e143a6033f
Use layer stacks from tech file in design class and throughout
2019-12-13 14:13:41 -08:00
Aditi Sinha
5b3846e1e5
Changed replica bitcell array to work with bank tests for non power of two rows
2019-12-08 13:24:39 +00:00
Matthew Guthaus
aca99b87bc
Fix config for tests 30
2019-11-16 22:22:30 +00:00
jsowash
8c33749223
Uncommented offset_all_coordinates.
2019-09-04 16:41:27 -07:00
jsowash
febc053587
Moved SRAM macro in LEF file to origin and removed poly.
2019-09-04 16:11:12 -07:00
jsowash
fbecb9bc02
Added poly to LEF files.
2019-09-04 14:06:17 -07:00
jsowash
d6e7047e2f
Added metal4 to lef files since it's now used with a wmask.
2019-09-04 13:04:51 -07:00
jsowash
4c40804b8f
Moved via in write driver up for 2 port.
2019-09-03 15:14:41 -07:00
jsowash
dd67490823
Changed routing to allow for 2 write port with write mask.
2019-09-03 14:43:03 -07:00
Matt Guthaus
69c5608b53
Allow gds to be written with supplies off. Fix extraction bug with new options.
2019-09-03 11:23:35 -07:00
jsowash
e3b42430bd
Changed max_gap_size_wmask to take into account column ffs.
2019-08-29 17:09:17 -07:00
jsowash
bbe235074c
Added max gap size for wmask and edited max gap size for data ff's to take into account m3 spacing.
2019-08-29 16:41:58 -07:00
jsowash
37116ce9d8
Increased spacing between wmask and data dffs.
2019-08-29 16:00:50 -07:00
jsowash
c1906ade3f
Removed A pin's via connection since it's created in the SRAM level and rearranged the SRAM flip flop creation.
2019-08-29 14:48:13 -07:00
jsowash
af3d2af0ec
Merge branch 'dev' into add_wmask
2019-08-29 12:56:11 -07:00
jsowash
f13c8eae8d
Moved column mux ff's to be horizontal with wmask flip flops and adjusted wmask AND array en pin location starting point.
2019-08-29 11:07:42 -07:00
Matt Guthaus
64fc771fc4
Simplify is not None
2019-08-22 15:02:52 -07:00
Matt Guthaus
ee2456f433
Merge branch 'add_wmask' into dev
2019-08-22 15:01:41 -07:00
jsowash
737e873923
Changed via direction for via1 in flip flops.
2019-08-21 14:49:54 -07:00
Matt Guthaus
9f54afbf2c
Fix capitalization in verilog golden files
2019-08-21 14:29:57 -07:00
jsowash
980760b724
Add preferred direction to via1, routed between supply lines in wmask AND array, and only uses m3 for channel route with a write mask.
2019-08-21 14:02:57 -07:00
Matt Guthaus
d0f04405a6
Convert capital names to lower case for consistency
2019-08-21 13:45:34 -07:00
jsowash
4f01eeb3c1
Combined changes to the pin locations and vias.
2019-08-21 12:36:53 -07:00
jsowash
c2015335b0
Fixed merge issues.
2019-08-21 11:54:22 -07:00
jsowash
4813c01d56
Moved dff's up and moved wmask_AND/wdriver pins left/down, respectively.
2019-08-21 11:50:28 -07:00
Matt Guthaus
b94af3e3fd
Add vias for new channel routes
2019-08-21 11:33:43 -07:00
jsowash
0cbc4a7acf
Moved wmask dff above data dff and changed channel route to m3/m4 for data and m1/m2 for wmask.
2019-08-21 10:07:20 -07:00
jsowash
c19bada8df
Performed clean up and added comments.
2019-08-19 08:57:05 -07:00
mrg
Jesse Cirimelli-Low
Bastian Koppelmann
Aditi Sinha
jsowash
jsowash
jsowash
jsowash
jsowash
jsowash
jsowash