 Matt Guthaus
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30fc81a1f0
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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mrg
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69fe050bad
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Refactor and cleanup router grids.
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2021-01-15 13:25:57 -08:00 |
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mrg
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6f5b7c0264
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Flatten bug fixed in Magic so don't flatten routes.
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2021-01-12 16:20:03 -08:00 |
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mrg
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ec6f0f1873
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Escape route to any side
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2021-01-06 09:40:32 -08:00 |
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mrg
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c89e156bfe
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Separate add pins and route pins so pins can block supply router.
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2020-12-23 10:49:47 -08:00 |
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mrg
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1885794016
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Only write drc/lvs scripts if drc/lvs is enabled
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2020-12-23 07:16:43 -08:00 |
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mrg
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94b1e729ab
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Don't add vias when placing dff array
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2020-12-22 17:08:53 -08:00 |
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mrg
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286ac635d6
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Escape router changes.
Rename exit router to escape router.
Perform supply and signal escape routing after channel and other routing.
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2020-12-22 16:35:05 -08:00 |
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mrg
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52119fe3b3
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Cleanup exit route. Pins are on perimeter mostly.
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2020-12-22 15:56:51 -08:00 |
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mrg
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ae1c889235
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Updates to IO signal router.
Route signals to perimeter using maze router.
Move IO pins without perimeter pins to M3 using add_io_pin (like add_power_pin).
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2020-12-22 09:39:58 -08:00 |
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mrg
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348001b1c8
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Supply tree uses signal grid. PEP8 cleanup.
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2020-12-21 13:51:50 -08:00 |
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mrg
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98250cf115
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Copy pins as rects before removing them.
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2020-12-21 13:47:05 -08:00 |
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mrg
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3c08dfcca5
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Enable single pin for vdd/gnd after supply router
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2020-12-18 11:09:10 -08:00 |
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mrg
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c0ab0af201
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Retry routes with expanding detour allowed.
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2020-12-17 11:39:17 -08:00 |
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mrg
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d5ed45dadf
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Make default router tree router
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2020-12-16 16:42:19 -08:00 |
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mrg
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f55b57033d
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Route col decoder address with data bits in channel
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2020-12-15 16:37:23 -08:00 |
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mrg
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878a9cee8a
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Add channel routes as flat instances to appease Magic extraction.
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2020-12-15 16:01:39 -08:00 |
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mrg
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6714e9fac0
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Only run DRC and LVS at SRAM level if not a unit test to reduce run time.
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2020-12-15 10:46:55 -08:00 |
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 Hunter Nichols
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84ba5c55d1
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Merged with dev
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2020-11-10 15:47:56 -08:00 |
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mrg
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57e708a6e1
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Add 200 cycles. Can be commented out or run for shorter.
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2020-11-09 15:20:36 -08:00 |
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mrg
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532492d5ae
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Output functional stimulus to output directory.
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2020-11-09 12:00:25 -08:00 |
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mrg
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10542d6cc3
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Output DRC and LVS run files to output directory.
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2020-11-09 11:12:31 -08:00 |
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mrg
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29ac541b28
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Refactor dynamic cell name to utilize base class
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2020-11-03 13:18:46 -08:00 |
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mrg
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da721a677d
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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mrg
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fa89b73ef8
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PR from mithro + other changable GDS file names
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2020-11-02 16:00:16 -08:00 |
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Hunter Nichols
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12a8531248
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Allowed for OPTS writeback of words_per_row if automatically generated during generation.
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2020-10-21 03:02:39 -07:00 |
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mrg
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c2629edc1b
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Allow 16-way column mux
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2020-10-06 16:27:02 -07:00 |
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mrg
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1e24b780bb
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Initial pex sram test.
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2020-10-02 13:32:52 -07:00 |
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mrg
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b32c123dab
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PEP8 cleanup. Un-hard-code bitcell layers. Remove dead variable.
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2020-10-01 11:10:18 -07:00 |
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mrg
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18c8ad265e
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Unique name for sram channel routes
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2020-10-01 09:55:34 -07:00 |
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Matt Guthaus
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112d57d90a
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Enable riscv tests
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2020-09-30 12:39:40 -07:00 |
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mrg
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b147e8485c
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PEP8 formatting
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2020-09-29 16:52:27 -07:00 |
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mrg
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449a4c2660
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Exclude bitcells in other local areas not of interest
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2020-09-29 12:15:42 -07:00 |
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mrg
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d7e2340e62
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Lots of PEP8 cleanup. Refactor path graph to simulation class.
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2020-09-29 10:26:31 -07:00 |
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mrg
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88731ccd8e
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Fix rounding error for wmask with various word_size
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2020-09-28 09:53:01 -07:00 |
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Hunter Nichols
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af22e438f1
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Added option to output an extended configuration file that includes defaults.
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2020-09-08 18:40:39 -07:00 |
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Hunter Nichols
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73b2277daa
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Removed dead code related to older characterization scheme
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2020-08-27 17:30:58 -07:00 |
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mrg
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652f160aca
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Merge branch 'wlbuffer' into dev
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2020-08-25 15:50:08 -07:00 |
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mrg
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bd8bf9afd8
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Remove RBL label at top level of SRAM
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2020-08-25 14:42:21 -07:00 |
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mrg
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28bd93bf51
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Still working on array refactor
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2020-08-25 11:50:44 -07:00 |
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 jcirimel
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9cecf367ee
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Merge branch 'dev' into pex
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2020-08-17 17:49:41 -07:00 |
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jcirimel
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714b57d48e
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Merge branch 'dev' into pex
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2020-08-17 17:48:21 -07:00 |
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mrg
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60224b105f
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-08-17 14:20:34 -07:00 |
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mrg
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50525e70f4
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Fix up to SRAM level with new replica bitcell array ports.
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2020-08-13 14:29:10 -07:00 |
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mrg
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0bec6f0439
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Fix SRAM to use simulation spice instead of LVS spice
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2020-08-12 10:41:21 -07:00 |
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jcirimel
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02e65a00ef
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update pex to work with dev changes
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2020-08-03 17:14:34 -07:00 |
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 Bob Vanhoof
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9b8ef5ef57
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fix: generated pex file was not passed correctly to lib characterizer
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2020-08-03 10:16:12 +02:00 |
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mrg
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487027a9f2
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Fix pex file names
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2020-07-30 11:35:13 -07:00 |
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Matt Guthaus
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68387ec525
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Merge pull request #84 from bvhoof/CalibrePexFilesUpdate
calibrepex: file copy fix
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2020-07-30 08:40:35 -07:00 |
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mrg
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f23d2e36a7
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Don't obstruct control logic signals with dffs when no column mux.
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2020-07-29 10:31:18 -07:00 |
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