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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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1a97dfc63e29b52db7ebf579c1c1c2eefaea97c0
OpenRAM/compiler/sram
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Jesse Cirimelli-Low 1a97dfc63e syncronize bitline naming convention betwen bitcell and pbitcell
2020-01-27 11:50:43 +00:00
..
sram_1bank.py
fix s_en in stim
2020-01-16 12:16:49 -08:00
sram_2bank.py
Convert capital names to lower case for consistency
2019-08-21 13:45:34 -07:00
sram_base.py
syncronize bitline naming convention betwen bitcell and pbitcell
2020-01-27 11:50:43 +00:00
sram_config.py
Additional debug. Smaller psram func tests.
2019-08-05 13:53:14 -07:00
sram.py
Allow gds to be written with supplies off. Fix extraction bug with new options.
2019-09-03 11:23:35 -07:00
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