 mrg
|
aaa36bf5cf
|
Default to 2 threads only
|
2020-10-01 09:55:17 -07:00 |
|
|
mrg
|
d315ff18e5
|
Add num_threads to options. PEP8 cleanup.
|
2020-10-01 08:07:03 -07:00 |
|
|
mrg
|
b81cdab0d6
|
Use unique instance names for channel routes.
|
2020-10-01 07:43:06 -07:00 |
|
|
mrg
|
8ce23d7f17
|
Provide unique WL driver instance name
|
2020-10-01 07:17:32 -07:00 |
|
|
mrg
|
bd125e2ed3
|
Check for duplicate instance names.
|
2020-10-01 07:17:16 -07:00 |
|
|
Matt Guthaus
|
2b475670f7
|
Check for failed result in functional simulation
|
2020-09-30 12:40:07 -07:00 |
|
|
Matt Guthaus
|
112d57d90a
|
Enable riscv tests
|
2020-09-30 12:39:40 -07:00 |
|
|
mrg
|
f4e6a8895b
|
Update riscv unit test
|
2020-09-30 08:50:58 -07:00 |
|
 jcirimel
|
7cbf456a4f
|
sky130 rba done
|
2020-09-30 07:34:05 -07:00 |
|
|
mrg
|
b147e8485c
|
PEP8 formatting
|
2020-09-29 16:52:27 -07:00 |
|
|
mrg
|
066570bfeb
|
Fix length of write driver
|
2020-09-29 16:51:55 -07:00 |
|
|
mrg
|
8e908f016e
|
PEP8 formatting
|
2020-09-29 13:43:59 -07:00 |
|
|
mrg
|
bca69b24e3
|
Optional number of functional cycles
|
2020-09-29 13:43:54 -07:00 |
|
|
mrg
|
54890a8d77
|
Add new golden data
|
2020-09-29 13:43:34 -07:00 |
|
|
mrg
|
449a4c2660
|
Exclude bitcells in other local areas not of interest
|
2020-09-29 12:15:42 -07:00 |
|
|
mrg
|
0c280e062a
|
Fix func test with row/col of 0. PEP8 cleanup. Smaller global test case.
|
2020-09-29 11:35:58 -07:00 |
|
|
mrg
|
4b5bbe755f
|
PEP8 cleanup. Fix cur_slew bug.
|
2020-09-29 11:13:58 -07:00 |
|
|
mrg
|
9032bb9869
|
Add global wordline delay test
|
2020-09-29 10:28:57 -07:00 |
|
|
mrg
|
d7e2340e62
|
Lots of PEP8 cleanup. Refactor path graph to simulation class.
|
2020-09-29 10:26:31 -07:00 |
|
|
mrg
|
1eb8798bb6
|
Add global functional test
|
2020-09-28 16:12:09 -07:00 |
|
|
mrg
|
b2dab486fc
|
Add draft of path exclusion calls
|
2020-09-28 16:05:21 -07:00 |
|
|
mrg
|
4a987bef9a
|
Merge branch 'wlbuffer' into dev
|
2020-09-28 15:51:45 -07:00 |
|
|
mrg
|
159c04a25d
|
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
|
2020-09-28 15:51:35 -07:00 |
|
|
mrg
|
70c90ca7fb
|
Replica bitcell array bbox to include unused WL gnd pins.
|
2020-09-28 14:49:33 -07:00 |
|
|
mrg
|
9c6d8d7aed
|
Zjob to bottom.
|
2020-09-28 13:16:03 -07:00 |
|
|
mrg
|
5ab0d01779
|
Remove zjog and go with L shape.
|
2020-09-28 12:48:37 -07:00 |
|
|
mrg
|
d65eb16513
|
Zjog the WL enable. Min driver is 1.
|
2020-09-28 12:24:55 -07:00 |
|
|
mrg
|
6f06bb9dd5
|
Create sized RBL WL driver in port_address
|
2020-09-28 11:30:21 -07:00 |
|
|
mrg
|
88731ccd8e
|
Fix rounding error for wmask with various word_size
|
2020-09-28 09:53:01 -07:00 |
|
|
jcirimel
|
3dd72cdeac
|
progress with rba pin mismatch
|
2020-09-23 08:37:32 -07:00 |
|
|
jcirimel
|
17e6e5eb16
|
row end col done
|
2020-09-23 08:02:56 -07:00 |
|
|
jcirimel
|
5c263e0001
|
rep col done w/o power pins
|
2020-09-23 06:24:52 -07:00 |
|
|
jcirimel
|
7afe3ea52c
|
replica col arrangement done
|
2020-09-23 04:51:09 -07:00 |
|
|
jcirimel
|
7f8edf6d7c
|
fix replica bitcell col
|
2020-09-23 00:36:08 -07:00 |
|
|
jcirimel
|
efdc171b14
|
make split wl specific to each port
|
2020-09-23 00:08:34 -07:00 |
|
|
jcirimel
|
fb6a665514
|
removed references to technology name
|
2020-09-22 18:33:03 -07:00 |
|
|
jcirimel
|
de33ab3761
|
fix single port bitcell pattern
|
2020-09-22 15:08:53 -07:00 |
|
|
mrg
|
c7d32089f3
|
Create RBL wordline buffer with correct polarity.
|
2020-09-17 14:45:49 -07:00 |
|
|
jcirimel
|
559dfbc7a6
|
single port bitcell array done
|
2020-09-16 05:46:14 -07:00 |
|
|
mrg
|
392afd4d4b
|
Add unit test for hierarchical wordline.
|
2020-09-15 13:46:21 -07:00 |
|
|
mrg
|
11f2b6b809
|
Do not do final verification if supplies were not routed
|
2020-09-15 13:39:00 -07:00 |
|
|
mrg
|
e7ad22ff69
|
Separate WL via from bitell array to avoid grounded WLs
|
2020-09-15 13:38:28 -07:00 |
|
|
mrg
|
5e94d76127
|
Make global bitline only as wide as needed rather than whole array
|
2020-09-15 13:24:38 -07:00 |
|
|
mrg
|
aff3cd2aab
|
Update length of control bus
|
2020-09-15 09:49:00 -07:00 |
|
|
jcirimel
|
d22164bd48
|
single port progess
|
2020-09-14 18:11:38 -07:00 |
|
|
mrg
|
f25b6ffa61
|
Make control bus height of port data
|
2020-09-14 15:42:17 -07:00 |
|
|
mrg
|
7b24d1f012
|
Use pins for write_driver dimensions
|
2020-09-14 14:42:28 -07:00 |
|
|
mrg
|
55dd4d0c47
|
Global bitcell array working
|
2020-09-14 14:35:52 -07:00 |
|
|
mrg
|
deaaec1ede
|
Fix width of write enable with spare columns
|
2020-09-14 13:09:45 -07:00 |
|
|
mrg
|
c12720a93f
|
Extend pin correct length in new array.
|
2020-09-14 12:53:59 -07:00 |
|