luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
559dfbc7a67f4f6ffd9a33c61da4e578df736ec4
OpenRAM/compiler
T
History
jcirimel 559dfbc7a6 single port bitcell array done
2020-09-16 05:46:14 -07:00
..
.vscode
single port progess
2020-09-14 18:11:38 -07:00
base
single port progess
2020-09-14 18:11:38 -07:00
bitcells
single port progess
2020-09-14 18:11:38 -07:00
characterizer
Merge branch 'dev' into pex
2020-08-17 17:49:41 -07:00
custom
single port progess
2020-09-14 18:11:38 -07:00
datasheet
Convert capital names to lower case for consistency
2019-08-21 13:45:34 -07:00
drc
PEP8 cleanup
2020-04-15 11:24:28 -07:00
example_configs
single port progess
2020-09-14 18:11:38 -07:00
gdsMill
single port progess
2020-09-14 18:11:38 -07:00
modules
single port bitcell array done
2020-09-16 05:46:14 -07:00
pgates
merge dev
2020-08-19 14:25:41 -07:00
riscv
single port progess
2020-09-14 18:11:38 -07:00
router
Changes to simplify metal preferred directions and pitches.
2020-05-10 11:32:45 -07:00
scmos_run
single port progess
2020-09-14 18:11:38 -07:00
sram
Merge branch 'wlbuffer' into dev
2020-08-25 15:50:08 -07:00
sram_0.8
single port progess
2020-09-14 18:11:38 -07:00
sram_0.01
single port progess
2020-09-14 18:11:38 -07:00
sram_0.05
single port progess
2020-09-14 18:11:38 -07:00
sram_0.75
single port progess
2020-09-14 18:11:38 -07:00
sram_0.78
single port progess
2020-09-14 18:11:38 -07:00
sram_0.85
single port progess
2020-09-14 18:11:38 -07:00
temp
single port progess
2020-09-14 18:11:38 -07:00
tests
single port progess
2020-09-14 18:11:38 -07:00
verify
Merge branch 'wlbuffer' into dev
2020-08-25 15:50:08 -07:00
b3v3_1check.log
single port progess
2020-09-14 18:11:38 -07:00
b3v32check.log
single port progess
2020-09-14 18:11:38 -07:00
big.log
single port progess
2020-09-14 18:11:38 -07:00
debug.py
DRC/LVS and errors fixes.
2020-06-30 07:16:05 -07:00
gen_stimulus.py
Fixed errors in extra rows characterization
2020-03-22 20:54:49 +00:00
globals.py
OpenRAM 1.1.6
2020-07-13 16:26:25 -07:00
Makefile
Clean up Makefile for unit tests
2018-12-05 12:58:10 -08:00
missing_pin.gds
single port progess
2020-09-14 18:11:38 -07:00
openram.py
Add words_per_row and others in config file.
2020-07-13 12:37:56 -07:00
options.py
Add words_per_row and others in config file.
2020-07-13 12:37:56 -07:00
profile.dat
single port progess
2020-09-14 18:11:38 -07:00
run_profile.sh
Convert pin map to a set for faster membership.
2019-04-01 15:45:44 -07:00
run.sh
single port progess
2020-09-14 18:11:38 -07:00
sram_2_16_scn4m_subm_FF_5p0V_25C.lib
single port progess
2020-09-14 18:11:38 -07:00
sram_2_16_scn4m_subm_SS_5p0V_25C.lib
single port progess
2020-09-14 18:11:38 -07:00
sram_2_16_scn4m_subm_TT_5p0V_25C.lib
single port progess
2020-09-14 18:11:38 -07:00
sram_2_16_scn4m_subm.gds
single port progess
2020-09-14 18:11:38 -07:00
sram_2_16_scn4m_subm.html
single port progess
2020-09-14 18:11:38 -07:00
sram_2_16_scn4m_subm.lef
single port progess
2020-09-14 18:11:38 -07:00
sram_2_16_scn4m_subm.log
single port progess
2020-09-14 18:11:38 -07:00
sram_2_16_scn4m_subm.py
single port progess
2020-09-14 18:11:38 -07:00
sram_2_16_scn4m_subm.sp
single port progess
2020-09-14 18:11:38 -07:00
sram_2_16_scn4m_subm.v
single port progess
2020-09-14 18:11:38 -07:00
sram_8_128_scn4m_subm_FF_5p0V_25C.lib
single port progess
2020-09-14 18:11:38 -07:00
sram_8_128_scn4m_subm_SS_5p0V_25C.lib
single port progess
2020-09-14 18:11:38 -07:00
sram_8_128_scn4m_subm_TT_5p0V_25C.lib
single port progess
2020-09-14 18:11:38 -07:00
sram_8_128_scn4m_subm.html
single port progess
2020-09-14 18:11:38 -07:00
sram_8_128_scn4m_subm.log
single port progess
2020-09-14 18:11:38 -07:00
sram_8_128_scn4m_subm.py
single port progess
2020-09-14 18:11:38 -07:00
sram_8_128_scn4m_subm.sp
single port progess
2020-09-14 18:11:38 -07:00
sram_8_128_scn4m_subm.v
single port progess
2020-09-14 18:11:38 -07:00
sram_16_256_scn4m_subm_FF_5p0V_25C.lib
single port progess
2020-09-14 18:11:38 -07:00
sram_16_256_scn4m_subm_SS_5p0V_25C.lib
single port progess
2020-09-14 18:11:38 -07:00
sram_16_256_scn4m_subm_TT_5p0V_25C.lib
single port progess
2020-09-14 18:11:38 -07:00
sram_16_256_scn4m_subm.html
single port progess
2020-09-14 18:11:38 -07:00
sram_16_256_scn4m_subm.log
single port progess
2020-09-14 18:11:38 -07:00
sram_16_256_scn4m_subm.py
single port progess
2020-09-14 18:11:38 -07:00
sram_16_256_scn4m_subm.sp
single port progess
2020-09-14 18:11:38 -07:00
sram_16_256_scn4m_subm.v
single port progess
2020-09-14 18:11:38 -07:00
sram_32_128_scn4m_subm_FF_5p0V_25C.lib
single port progess
2020-09-14 18:11:38 -07:00
sram_32_128_scn4m_subm_SS_5p0V_25C.lib
single port progess
2020-09-14 18:11:38 -07:00
sram_32_128_scn4m_subm_TT_5p0V_25C.lib
single port progess
2020-09-14 18:11:38 -07:00
sram_32_128_scn4m_subm.html
single port progess
2020-09-14 18:11:38 -07:00
sram_32_128_scn4m_subm.log
single port progess
2020-09-14 18:11:38 -07:00
sram_32_128_scn4m_subm.py
single port progess
2020-09-14 18:11:38 -07:00
sram_32_128_scn4m_subm.sp
single port progess
2020-09-14 18:11:38 -07:00
sram_32_128_scn4m_subm.v
single port progess
2020-09-14 18:11:38 -07:00
sram_factory.py
Auto-generate port dependent cell names.
2020-06-05 15:09:22 -07:00
view_profile.py
Remove some flake8 errors/warnings.
2019-10-02 23:26:02 +00:00