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base
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Merge branch 'dev' into wlbuffer
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2020-09-10 13:05:14 -07:00 |
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bitcells
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update to new metal stack names
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2020-07-31 05:27:19 -07:00 |
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characterizer
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Fixed import in simulation and fixed names in functional
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2020-09-04 02:24:18 -07:00 |
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custom
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Removed dead code related to older characterization scheme
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2020-08-27 17:30:58 -07:00 |
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datasheet
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Convert capital names to lower case for consistency
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2019-08-21 13:45:34 -07:00 |
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drc
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PEP8 cleanup
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2020-04-15 11:24:28 -07:00 |
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example_configs
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Fix 1w/1r example
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2020-07-23 14:17:13 -07:00 |
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gdsMill
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added purposes to addText(), removed reference to specific tech from gdsMill
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2020-02-19 16:26:52 -08:00 |
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modules
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Separate WL via from bitell array to avoid grounded WLs
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2020-09-15 13:38:28 -07:00 |
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pgates
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Removed dead code related to older characterization scheme
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2020-08-27 17:30:58 -07:00 |
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router
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Changes to simplify metal preferred directions and pitches.
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2020-05-10 11:32:45 -07:00 |
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sram
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Added option to output an extended configuration file that includes defaults.
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2020-09-08 18:40:39 -07:00 |
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tests
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Global bitcell array working
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2020-09-14 14:35:52 -07:00 |
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verify
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Merge branch 'wlbuffer' into dev
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2020-08-25 15:50:08 -07:00 |
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Makefile
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Clean up Makefile for unit tests
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2018-12-05 12:58:10 -08:00 |
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debug.py
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DRC/LVS and errors fixes.
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2020-06-30 07:16:05 -07:00 |
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gen_stimulus.py
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Fixed errors in extra rows characterization
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2020-03-22 20:54:49 +00:00 |
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globals.py
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OpenRAM 1.1.6
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2020-07-13 16:26:25 -07:00 |
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openram.py
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Add words_per_row and others in config file.
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2020-07-13 12:37:56 -07:00 |
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options.py
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Added option to output an extended configuration file that includes defaults.
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2020-09-08 18:40:39 -07:00 |
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run_profile.sh
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Convert pin map to a set for faster membership.
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2019-04-01 15:45:44 -07:00 |
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sram_factory.py
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Auto-generate port dependent cell names.
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2020-06-05 15:09:22 -07:00 |
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view_profile.py
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Remove some flake8 errors/warnings.
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2019-10-02 23:26:02 +00:00 |
e7ad22ff69