mrg c12720a93f Extend pin correct length in new array.

2020-09-14 12:53:59 -07:00

..

base

Merge branch 'dev' into wlbuffer

2020-09-10 13:05:14 -07:00

bitcells

update to new metal stack names

2020-07-31 05:27:19 -07:00

characterizer

Fixed import in simulation and fixed names in functional

2020-09-04 02:24:18 -07:00

custom

Removed dead code related to older characterization scheme

2020-08-27 17:30:58 -07:00

datasheet

Convert capital names to lower case for consistency

2019-08-21 13:45:34 -07:00

drc

PEP8 cleanup

2020-04-15 11:24:28 -07:00

example_configs

Fix 1w/1r example

2020-07-23 14:17:13 -07:00

gdsMill

added purposes to addText(), removed reference to specific tech from gdsMill

2020-02-19 16:26:52 -08:00

modules

Extend pin correct length in new array.

2020-09-14 12:53:59 -07:00

pgates

Removed dead code related to older characterization scheme

2020-08-27 17:30:58 -07:00

router

Changes to simplify metal preferred directions and pitches.

2020-05-10 11:32:45 -07:00

sram

Added option to output an extended configuration file that includes defaults.

2020-09-08 18:40:39 -07:00

tests

Fix pbitcell array test

2020-09-09 12:02:09 -07:00

verify

Merge branch 'wlbuffer' into dev

2020-08-25 15:50:08 -07:00

debug.py

DRC/LVS and errors fixes.

2020-06-30 07:16:05 -07:00

gen_stimulus.py

Fixed errors in extra rows characterization

2020-03-22 20:54:49 +00:00

globals.py

OpenRAM 1.1.6

2020-07-13 16:26:25 -07:00

Makefile

Clean up Makefile for unit tests

2018-12-05 12:58:10 -08:00

openram.py

Add words_per_row and others in config file.

2020-07-13 12:37:56 -07:00

options.py

Added option to output an extended configuration file that includes defaults.

2020-09-08 18:40:39 -07:00

run_profile.sh

Convert pin map to a set for faster membership.

2019-04-01 15:45:44 -07:00

sram_factory.py

Auto-generate port dependent cell names.

2020-06-05 15:09:22 -07:00

view_profile.py

Remove some flake8 errors/warnings.

2019-10-02 23:26:02 +00:00