mrg 70c90ca7fb Replica bitcell array bbox to include unused WL gnd pins.		2020-09-28 14:49:33 -07:00
..
base	Create RBL wordline buffer with correct polarity.	2020-09-17 14:45:49 -07:00
bitcells	update to new metal stack names	2020-07-31 05:27:19 -07:00
characterizer	Fixed import in simulation and fixed names in functional	2020-09-04 02:24:18 -07:00
custom	Removed dead code related to older characterization scheme	2020-08-27 17:30:58 -07:00
datasheet	…
drc	PEP8 cleanup	2020-04-15 11:24:28 -07:00
example_configs	Fix 1w/1r example	2020-07-23 14:17:13 -07:00
gdsMill	…
modules	Replica bitcell array bbox to include unused WL gnd pins.	2020-09-28 14:49:33 -07:00
pgates	Zjog the WL enable. Min driver is 1.	2020-09-28 12:24:55 -07:00
router	Changes to simplify metal preferred directions and pitches.	2020-05-10 11:32:45 -07:00
sram	Added option to output an extended configuration file that includes defaults.	2020-09-08 18:40:39 -07:00
tests	Create sized RBL WL driver in port_address	2020-09-28 11:30:21 -07:00
verify	Do not do final verification if supplies were not routed	2020-09-15 13:39:00 -07:00
Makefile	…
debug.py	DRC/LVS and errors fixes.	2020-06-30 07:16:05 -07:00
gen_stimulus.py	…
globals.py	OpenRAM 1.1.6	2020-07-13 16:26:25 -07:00
openram.py	Add words_per_row and others in config file.	2020-07-13 12:37:56 -07:00
options.py	Zjog the WL enable. Min driver is 1.	2020-09-28 12:24:55 -07:00
run_profile.sh	…
sram_factory.py	Auto-generate port dependent cell names.	2020-06-05 15:09:22 -07:00
view_profile.py	…