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OpenRAM
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3081 Commits

Author SHA1 Message Date
Hunter Nichols 53503f40d2 Changed util functions to expect multiple outputs in data. Changed train models to account for multiple outputs when reading in data. 2021-05-24 12:03:26 -07:00
Hunter Nichols a4cb539f72 Removed old sim data csvs and added a new version. Added a default check for LAS in data extraction. 2021-05-24 10:44:46 -07:00
Jesse Cirimelli-Low f9eae3fb80 route bias pisn 2021-05-24 02:42:04 -07:00
mrg 9c01e22281 Prioritize Xyce. 2021-05-21 12:05:10 -07:00
mrg f856a44376 Restrict to direct KLU solver 2021-05-21 12:04:26 -07:00
mrg fc17a1ff45 Xyce can be capital or lower case 2021-05-21 12:04:26 -07:00
mrg d51ec4fe45 Add Xyce tests 2021-05-21 12:04:26 -07:00
mrg eadf7eedc5 Prioritize Xyce to last until bugs resolved. 2021-05-21 10:01:37 -07:00
Hunter Nichols 4e40017fdc Added model configs adapted from OpenRAM Library 2021-05-20 15:26:24 -07:00
Hunter Nichols 41c8eeb23c Adjusted paths in makefile for generating data used in regression models 2021-05-20 13:05:16 -07:00
Hunter Nichols 269b698b0a Fixed issues with csv generation. Added regex parsing to determine corners from datasheet. 2021-05-18 23:41:16 -07:00
mrg 7c001732b1 Add destination file as dot file 2021-05-18 14:54:13 -07:00
mrg 191b382171 Change magic to use OPENRAM_MAGICRC if defined. 2021-05-18 13:27:11 -07:00
Hunter Nichols 36b1bc1284 Added script to extract data from datasheet output and store in CSV. 2021-05-17 14:04:20 -07:00
Hunter Nichols 0434e57609 Added target in makefile to run configs and store results in tech directory. 2021-05-17 14:03:32 -07:00
mrg 3abebe4068 Add hierarchical seperator option to work with Xyce measurements. 2021-05-14 16:16:25 -07:00
mrg 7534610cdd Add MPI capability for Xyce threading. 2021-05-14 11:45:37 -07:00
mrg 507ad9f33d Change sim threads to 3. 2021-05-14 11:45:10 -07:00
mrg 67a67111a6 Initial Xyce support. 2021-05-14 11:28:29 -07:00
mrg 3959cf73d1 Remove setup/hold measure and compute it directly. 2021-05-14 10:11:14 -07:00
mrg 9555b52aaa Remove setup/hold measure and compute it directly. 2021-05-14 10:01:10 -07:00
Jesse Cirimelli-Low 0ba229afe5 Merge branch 'dev' into laptop_checkpoint 2021-05-07 19:06:17 -07:00
Jesse Cirimelli-Low e5662180e8 single port 20 series tests running 2021-05-07 18:44:45 -07:00
Jesse Cirimelli-Low 6d8411d19f use consistent amp spacing 2021-05-07 11:29:43 -07:00
mrg d43edd95e4 Update golden tests for verilog 2021-05-06 19:56:22 -07:00
mrg 57c58ce4a5 Always route data dff on m3 stack. 2021-05-06 17:14:39 -07:00
mrg 453f260ca2 Add commented save npz file for intern 2021-05-06 17:14:27 -07:00
mrg e995e61ea4 Fix Verilog module typo. Adjust RBL route. 2021-05-06 14:32:47 -07:00
mrg c057490923 Delay chain should have same height cells as control logic to align supplies. 2021-05-05 15:45:28 -07:00
mrg 789a8a1cf0 Update golden verilog results 2021-05-05 15:37:27 -07:00
mrg f677c8a88d Fix predecoder offset after relocating bank offset 2021-05-05 14:44:05 -07:00
mrg 120c4de5ad Fix placement of delay chain to align with control logic rows. 2021-05-05 14:21:53 -07:00
mrg b3948121df Default supply routing is tree. 2021-05-05 14:04:24 -07:00
mrg f48b0b8f41 Add left stripe power routes to tree router as option. 2021-05-05 13:45:12 -07:00
mrg d3f4810d1b Add error with zero length labels on GDS write. 2021-05-05 13:44:31 -07:00
mrg 2243761500 Must transitively cut blockages until no more. 2021-05-05 13:44:06 -07:00
Hunter Nichols 16904496ac Made path delays write out to the extended OPTS file. 2021-05-05 01:14:54 -07:00
mrg 19ea33d43d Move delay line module down. 2021-05-04 16:42:42 -07:00
Jesse Cirimelli-Low 1b53d12df2 don't double count spare col 2021-05-04 01:52:51 -07:00
Jesse Cirimelli-Low d0e9de1f13 fix port data spare col 2021-05-04 00:41:20 -07:00
Jesse Cirimelli-Low 93b264bc4c allow spare col number override 2021-05-03 21:59:05 -07:00
Jesse Cirimelli-Low a7d0a1ef3a remove breakpoint 2021-05-03 16:54:54 -07:00
Jesse Cirimelli-Low 14e087a5eb offset bank coordinates 2021-05-03 15:51:53 -07:00
mrg a0e263b14a Add vdd/gnd pins to the side. 2021-05-03 15:14:15 -07:00
Jesse Cirimelli-Low 4377619bf6 fixed port_data typo 2021-05-03 14:39:51 -07:00
Jesse Cirimelli-Low 31364e508e uncomment test (passing) 2021-05-03 13:08:04 -07:00
Jesse Cirimelli-Low d3199ea70e Merge branch 'dev' into laptop_checkpoint 2021-05-03 12:53:31 -07:00
Jesse Cirimelli-Low 64b1946d6e sky130 singlebank drc clean 2021-05-03 12:52:07 -07:00
Jesse Cirimelli-Low 3a3da9e0d7 56 drc errors on col mux 1port 2021-05-02 21:49:09 -07:00
mrg 98fb34c44c Add conditional power pins to Verilog model. 2021-04-30 14:15:32 -07:00
mrg fc6e6e1ec7 Add via when write driver supply is different layer 2021-04-28 15:16:26 -07:00
mrg 03e0c14ab2 Move write driver supply to m1 rather than pin layer 2021-04-28 10:13:33 -07:00
Jesse Cirimelli-Low 33e8bce79d dynamic predecode working 2021-04-25 01:22:36 -07:00
Jesse Cirimelli-Low 6ea4bdc5e5 Merge branch 'dev' into laptop_checkpoint 2021-04-23 22:50:23 -07:00
Jesse Cirimelli-Low 4ea0fcd068 support multi cell wide precharge cells 2021-04-23 22:49:29 -07:00
mrg 467aaa708d Add noninverting logic function to custom decoder cells. 2021-04-22 16:13:54 -07:00
mrg d018963866 Specify ImportError to see other errors 2021-04-22 16:13:32 -07:00
mrg 01f4ad7a11 Add sky130 config examples 2021-04-22 13:53:23 -07:00
mrg a111ecb74c Fix extra indent that made openlane fail. 2021-04-22 13:05:51 -07:00
mrg 35fcb3f631 Abstracted LEF added. Params for array wordline layers. 2021-04-22 09:44:25 -07:00
mrg 15b0583ff2 Add custom parameter for wordline layer 2021-04-22 09:42:49 -07:00
Hunter Nichols b8c7fcf182 Removed measurement check which conflicts with multiport memories 2021-04-21 15:53:27 -07:00
mrg 419836411c Fix missing via for global wordlines. 2021-04-21 11:33:18 -07:00
mrg f45efe3db6 Abstracted LEF added. Params for array wordline layers. 2021-04-21 11:04:01 -07:00
mrg 584349c911 Add custom parameter for wordline layer 2021-04-21 11:04:01 -07:00
mrg 9b40102bbb v1.1.15 2021-04-19 11:54:35 -07:00
mrg 439003e203 Respect the bus spacing parameter in predecoder. 2021-04-19 10:51:16 -07:00
Hunter Nichols 5dad0f2c0e Merged with dev, fixed import conflict in lib 2021-04-18 23:59:35 -07:00
mrg 5b556e6ef5 Update unit test results with new Verilog models. 2021-04-15 15:48:20 -07:00
mrg aa5e1fd168 Merge remote-tracking branch 'olofk/verilog_model_features' into dev 2021-04-15 14:41:56 -07:00
Olof Kindgren 688a1f1e60 Add HOLD_DELAY parameter for dout in verilog model 
Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>
 2021-04-15 22:39:49 +02:00
Olof Kindgren 1d657abebc Add VERBOSE parameter to generated verilog model 
This allows disabling the $display commands that are generated for every
read and write access to the model. The verilog output has been tested
with the following example script

from compiler.base.verilog import verilog

v = verilog()

v.num_words = 256
v.word_size = 32
v.write_size = 8
v.name = "sky130_sram_1kbyte_1rw1r_32x256_8"
v.all_ports = [0,1]
v.readwrite_ports = [0]
v.read_ports = [0,1]
v.write_ports = [0]
v.addr_size=8

v.verilog_write("mymodule.v")

Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>
 2021-04-15 22:33:57 +02:00
Jesse Cirimelli-Low e976c4043b Merge branch 'dev' into laptop_checkpoint 2021-04-14 15:58:06 -07:00
Jesse Cirimelli-Low 2f1d7b879f make bank compatable with sky130 2021-04-14 15:09:25 -07:00
mrg 41226087ba Use separate mXp pin layer if it exists 2021-04-14 13:55:21 -07:00
mrg 3eed6bb8ff Check for None before checking DRC tool 2021-04-14 11:07:38 -07:00
mrg a730fd0f10 Use magic for LEF abstract. Fix supply perimter pin. 2021-04-14 10:01:43 -07:00
mrg 0e48e020c1 Use pins in computing bbox offsets 2021-04-13 16:24:28 -07:00
mrg e706f776eb Offset macro to 0,0 which was accidentally comented by a PR 2021-04-13 16:24:13 -07:00
mrg b510925bdb Enable pruning by default (except on unit tests) 2021-04-07 16:08:29 -07:00
mrg 61b1b90dd3 Use built in binary conversion. Improve spare debug output. 2021-04-07 16:08:29 -07:00
mrg 229b0059c4 Add perimeter margin to expand pins outside perimeter for OpenRoad router. 2021-04-07 16:08:29 -07:00
mrg 5843aa037c Update functional test to use spare columns separately. 
Fix no spare columns data width error.
 2021-04-07 16:08:24 -07:00
mrg 0a02f635ad Remove lvs_write from sram 2021-04-07 16:08:24 -07:00
mrg d609e4ea04 Reimplement trim options (except on unit tests). 
Allow trim netlist to be used for delay and functional simulation.
Each class implements a "trim_insts" set of instances that can be removed.
By default far left, right, top and bottom cells in the bitcell arrays are kept.

Use lvs option in sp_write

Fix lvs option in sram.
 2021-04-07 16:07:56 -07:00
mrg 31d3e6cb26 Change LWL layers 2021-04-07 16:07:56 -07:00
mrg e0024fa79a Add verbosity to error output 2021-04-07 16:07:56 -07:00
mrg bd28a7a93b Merge branch 'sky130_fixes' into dev 2021-04-01 16:48:22 -07:00
mrg 014c95f761 Add accounting output to ngspice 2021-04-01 16:48:15 -07:00
mrg c7f99aef2c Add functional comment to aid debugging checks. 2021-03-31 12:14:20 -07:00
mrg 7e29dd7ff2 Reduce verbosity of routing info 2021-03-31 09:38:06 -07:00
mrg b9086dbbe5 Add unit test times to output. 2021-03-26 06:56:58 -07:00
mrg 6e2f60353c Add wells to driver stages. Remove unnecessary height/center in control logic. 2021-03-25 10:00:24 -07:00
mrg 4a40e96f6d Control logic route changes. 
Move wl_en to top control signal.
Route wl_en directly to port_address.
Reorder input bus to bank.
 2021-03-24 14:32:10 -07:00
mrg e144f03b23 Add status for supply routing. 2021-03-24 11:15:59 -07:00
mrg fae72ca993 Test new archive options for github actions. 2021-03-23 13:06:36 -07:00
mrg 7b270514e1 Update multithreaded regression. 
Only do 2 threads for 30 tests.
Don't archive results since they are purged anyways.
16 threads for regression.
Purge temp during regression.
 2021-03-23 10:45:56 -07:00
mrg 671470f5f2 Skywater changes. 
Default 1 thread and no temp subdirectory.
Add skywater setup/hold golden data
Add CLI option for simulation threads (-m)
Add compatibility mode option and nomodcheck for ngspice to speed up sky130 model loading.
Make subdir when using default /tmp dir.
Pass num_threads so temp subdirs are created.
 2021-03-22 15:48:14 -07:00
Hunter Nichols 6f01ab4792 Added simulation time modeling to regression model. 2021-03-22 12:55:29 -07:00
Hunter Nichols 208586a8e8 Added simulation time in the datasheet 2021-03-22 12:21:10 -07:00