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Add VERBOSE parameter to generated verilog model 

This allows disabling the $display commands that are generated for every
read and write access to the model. The verilog output has been tested
with the following example script

from compiler.base.verilog import verilog

v = verilog()

v.num_words = 256
v.word_size = 32
v.write_size = 8
v.name = "sky130_sram_1kbyte_1rw1r_32x256_8"
v.all_ports = [0,1]
v.readwrite_ports = [0]
v.read_ports = [0,1]
v.write_ports = [0]
v.addr_size=8

v.verilog_write("mymodule.v")

Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>
This commit is contained in:
Olof Kindgren 2021-04-15 22:33:57 +02:00
parent 608e4b81f1
commit 1d657abebc
1 changed files with 5 additions and 4 deletions
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9
compiler/base/verilog.py
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@ -61,6 +61,7 @@ class verilog:
self.vf.write(" parameter RAM_DEPTH = 1 << ADDR_WIDTH;\n")
self.vf.write(" // FIXME: This delay is arbitrary.\n")
self.vf.write(" parameter DELAY = 3 ;\n")
self.vf.write(" parameter VERBOSE = 1 ; //Set to 0 to only display warnings\n")
self.vf.write("\n")
for port in self.all_ports:
@ -130,19 +131,19 @@ class verilog:
if port in self.read_ports:
self.vf.write(" dout{0} = {1}'bx;\n".format(port, self.word_size))
if port in self.readwrite_ports:
self.vf.write(" if ( !csb{0}_reg && web{0}_reg ) \n".format(port))
self.vf.write(" if ( !csb{0}_reg && web{0}_reg && VERBOSE ) \n".format(port))
self.vf.write(" $display($time,\" Reading %m addr{0}=%b dout{0}=%b\",addr{0}_reg,mem[addr{0}_reg]);\n".format(port))
elif port in self.read_ports:
self.vf.write(" if ( !csb{0}_reg ) \n".format(port))
self.vf.write(" if ( !csb{0}_reg && VERBOSE ) \n".format(port))
self.vf.write(" $display($time,\" Reading %m addr{0}=%b dout{0}=%b\",addr{0}_reg,mem[addr{0}_reg]);\n".format(port))
if port in self.readwrite_ports:
self.vf.write(" if ( !csb{0}_reg && !web{0}_reg )\n".format(port))
self.vf.write(" if ( !csb{0}_reg && !web{0}_reg && VERBOSE )\n".format(port))
if self.write_size:
self.vf.write(" $display($time,\" Writing %m addr{0}=%b din{0}=%b wmask{0}=%b\",addr{0}_reg,din{0}_reg,wmask{0}_reg);\n".format(port))
else:
self.vf.write(" $display($time,\" Writing %m addr{0}=%b din{0}=%b\",addr{0}_reg,din{0}_reg);\n".format(port))
elif port in self.write_ports:
self.vf.write(" if ( !csb{0}_reg )\n".format(port))
self.vf.write(" if ( !csb{0}_reg && VERBOSE )\n".format(port))
if self.write_size:
self.vf.write(" $display($time,\" Writing %m addr{0}=%b din{0}=%b wmask{0}=%b\",addr{0}_reg,din{0}_reg,wmask{0}_reg);\n".format(port))
else: