mirror of https://github.com/VLSIDA/OpenRAM.git
Add noninverting logic function to custom decoder cells.
This commit is contained in:
parent
d018963866
commit
467aaa708d
|
|
@ -70,3 +70,7 @@ class nand2_dec(design.design):
|
|||
"""
|
||||
self.add_graph_edges(graph, port_nets)
|
||||
|
||||
def is_non_inverting(self):
|
||||
"""Return input to output polarity for module"""
|
||||
|
||||
return False
|
||||
|
|
|
|||
|
|
@ -70,3 +70,7 @@ class nand3_dec(design.design):
|
|||
"""
|
||||
self.add_graph_edges(graph, port_nets)
|
||||
|
||||
def is_non_inverting(self):
|
||||
"""Return input to output polarity for module"""
|
||||
|
||||
return False
|
||||
|
|
|
|||
|
|
@ -70,3 +70,7 @@ class nand4_dec(design.design):
|
|||
"""
|
||||
self.add_graph_edges(graph, port_nets)
|
||||
|
||||
def is_non_inverting(self):
|
||||
"""Return input to output polarity for module"""
|
||||
|
||||
return False
|
||||
|
|
|
|||
Loading…
Reference in New Issue