mirror of https://github.com/VLSIDA/OpenRAM.git
remove breakpoint
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@ -140,7 +140,6 @@ class sram_1bank(sram_base):
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# This includes 2 M2 pitches for the row addr clock line.
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# The delay line is aligned with the bitcell array while the control logic is aligned with the port_data
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# using the control_logic_center value.
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breakpoint()
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self.control_pos[port] = vector(-self.control_logic_insts[port].width - 2 * self.m2_pitch,
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self.bank.bank_array_ll.y - self.control_logic_insts[port].mod.control_logic_center.y)
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self.control_logic_insts[port].place(self.control_pos[port])
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