mirror of https://github.com/VLSIDA/OpenRAM.git
uncomment test (passing)
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@ -227,7 +227,7 @@ class column_mux(pgate.pgate):
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strap = factory.create(module_type=cell_props.strap_module, version=cell_props.strap_version)
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rbc_width = self.bitcell.width + strap.width
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else:
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rbc_width = cell.width
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rbc_width = self.bitcell.width
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# Add it to the right, aligned in between the two tx
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active_pos = vector(rbc_width,
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self.nmos_upper.by() - 0.5 * self.poly_space)
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@ -26,20 +26,20 @@ class single_bank_test(openram_test):
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c = sram_config(word_size=4,
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num_words=16)
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# c.words_per_row=1
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# factory.reset()
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# c.recompute_sizes()
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# debug.info(1, "No column mux")
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# a = factory.create("bank", sram_config=c)
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# self.local_check(a)
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c.words_per_row=1
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factory.reset()
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c.recompute_sizes()
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debug.info(1, "No column mux")
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a = factory.create("bank", sram_config=c)
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self.local_check(a)
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# c.num_words=32
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# c.words_per_row=2
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# factory.reset()
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# c.recompute_sizes()
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# debug.info(1, "Two way column mux")
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# a = factory.create("bank", sram_config=c)
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# self.local_check(a)
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c.num_words=32
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c.words_per_row=2
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factory.reset()
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c.recompute_sizes()
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debug.info(1, "Two way column mux")
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a = factory.create("bank", sram_config=c)
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self.local_check(a)
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c.num_words=64
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c.words_per_row=4
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@ -49,14 +49,14 @@ class single_bank_test(openram_test):
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a = factory.create("bank", sram_config=c)
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self.local_check(a)
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#c.word_size=2
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#c.num_words=128
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#c.words_per_row=8
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#factory.reset()
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#c.recompute_sizes()
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#debug.info(1, "Eight way column mux")
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#a = factory.create("bank", sram_config=c)
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#self.local_check(a)
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c.word_size=2
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c.num_words=128
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c.words_per_row=8
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factory.reset()
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c.recompute_sizes()
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debug.info(1, "Eight way column mux")
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a = factory.create("bank", sram_config=c)
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self.local_check(a)
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globals.end_openram()
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