OpenRAM

Commit Graph

Author	SHA1	Message	Date
samuelkcrow	b82213caff	use packages for imports in modules	2022-07-22 12:56:47 -07:00
samuelkcrow	5fa0689c02	fix drc error in wlen_row	2022-07-21 19:35:02 -07:00
samuelkcrow	12c58b0457	use spice names for delay chain output pins in layout	2022-07-21 19:35:02 -07:00
samuelkcrow	73021be8eb	copy vertical bus spacing from control_logic.py	2022-07-21 19:35:02 -07:00
samuelkcrow	2611468dd7	replace route_supply with route supplies from control_logic.py	2022-07-21 19:35:02 -07:00
samuelkcrow	9182ad7c61	add m4 spacing for route_rails same as control_logic.py	2022-07-21 19:35:02 -07:00
samuelkcrow	7f52e63aca	route glitch3 to inverter on wen row	2022-07-21 19:35:02 -07:00
samuelkcrow	231dca5b51	route w_en A and B inputs via M3, fix delay chain outputs connection to vertical bus	2022-07-21 19:35:02 -07:00
samuelkcrow	fd7a7c2564	routing mistake in route_wlen	2022-07-21 19:35:02 -07:00
samuelkcrow	1e1ec54275	fix indentation errors, typos, and missing iterator	2022-07-21 19:35:02 -07:00
samuelkcrow	1d6bd78612	multi-delay layout pins and routing for them in control logic	2022-07-21 19:35:01 -07:00
samuelkcrow	d7b1368115	all route functions except for delay	2022-07-21 19:35:01 -07:00
samuelkcrow	63ea1588c1	more consise glitch names, remove pre_sen from vertical bus, typo in glitch2 placement	2022-07-21 19:35:01 -07:00
samuelkcrow	0a3c1dd9b8	remove pre_sen entirely, move inverter to wl_en row, complete placement functions	2022-07-21 19:35:01 -07:00
samuelkcrow	7b4af87fda	remove the cs_buf function call... smh	2022-07-21 19:35:01 -07:00
samuelkcrow	5edb511dab	try it without pre_sen	2022-07-21 19:35:01 -07:00
samuelkcrow	71f241f660	remove remaining cs_buf functions	2022-07-21 19:35:01 -07:00
samuelkcrow	67c1560df0	forgot other place with cs_buf	2022-07-21 19:35:01 -07:00
samuelkcrow	fede082b80	cs instead of cs_buf now that everything else is working	2022-07-21 19:35:01 -07:00
samuelkcrow	30b9c2fc25	remove glitch inverters from placement functions, move glitch1 to pen row	2022-07-21 19:35:01 -07:00
samuelkcrow	606260dd68	use odd number inverter chains from delay chain for delay instead of external inverters	2022-07-21 19:35:01 -07:00
samuelkcrow	b9b57ab6b3	double length of delay chain as well	2022-07-21 19:35:01 -07:00
samuelkcrow	06254fae72	forgot to multiply all delay chain pinouts by 2 because of previous design that only exposed pins for even numbered inverters in delay chain... oops	2022-07-21 19:35:01 -07:00
samuelkcrow	7d4b718344	add most functions needed for delay control logic, fix multi-delay pin order issue	2022-07-21 19:35:01 -07:00
samuelkcrow	45239ca2a9	use cs_buf for sense amp on r ports instead of cs	2022-07-21 19:35:01 -07:00
samuelkcrow	c4138c9f9b	typo in cs buf netlist function	2022-07-21 19:35:01 -07:00
samuelkcrow	11ea82e782	check delay chain pinout list, add cs_buf to control logic	2022-07-21 19:35:01 -07:00
samuelkcrow	78013d32b7	hard-code multi-delay stages	2022-07-21 19:35:01 -07:00
samuelkcrow	62a65f8053	all remaining spice for delay control	2022-07-21 19:35:01 -07:00
samuelkcrow	66502fc5dc	new control logic module with no more rbl logic, added glitches so far	2022-07-21 19:35:01 -07:00

30 Commits