9231ad51a4
vhdlpp: generics without a default value are set to 1'bx.
2015-05-19 22:40:56 +02:00
25458b8cc2
vhdlpp: inout direction for ports.
2015-05-19 22:40:56 +02:00
515ab40ffe
vhdlpp: Special handling for string type emission.
2015-05-19 22:40:56 +02:00
ddc204391e
vhdlpp: Add 'sub' prefix for subtypes while emitting packages.
2015-05-19 22:40:55 +02:00
a33bbecc98
vhdlpp: VTypeRange::write_to_stream uses to/downto depending on the range boundaries.
2015-05-19 22:40:55 +02:00
7442c14689
Merge pull request #67 from orsonmmz/boolean
...
Boolean & asserts for vhdlpp
2015-05-13 09:57:18 -07:00
7db01d8ded
vhdlpp: ScopeBase::is_enum_name() returns VTypeEnum* instead of bool.
2015-05-07 16:28:30 +02:00
e4694cb6cb
vhdlpp: Changed emitted type from 'bool' to 'bit'.
2015-05-07 16:09:02 +02:00
08e5aa021a
vhdlpp: Emits typedef for boolean type.
2015-05-07 16:09:02 +02:00
4304fd503e
vhdlpp: and_reduce() and or_reduce() functions.
2015-05-06 10:03:02 +02:00
5438464d67
vhdlpp: Support for reports & asserts.
2015-05-06 10:02:56 +02:00
6df2979998
vhdlpp: Added missing std_logic values in ExpChar and ExpString::emit().
2015-05-06 09:55:08 +02:00
9de4ced133
vhdlpp: Stop compilation on invalid attributes.
2015-05-06 09:55:08 +02:00
c8fe897446
vhdlpp: and_reduce() and or_reduce() functions.
2015-04-24 13:46:30 +02:00
5101b3b64b
vhdlpp: Boolean values handled without using keywords.
2015-04-24 13:39:41 +02:00
bed5ee4529
vhdlpp: Handle 'severity' statements without using keywords.
2015-04-24 13:39:41 +02:00
7c0a191626
vhdlpp: Handle true/false values.
2015-04-23 11:58:40 +02:00
cfa43c7742
vhdlpp: Support for reports & asserts.
2015-04-23 11:58:40 +02:00
a5138e238f
vhdlpp: Added missing std_logic values in ExpChar and ExpString::emit().
2015-04-23 11:57:27 +02:00
d352d8ead3
vhdlpp: Stop compilation on invalid attributes.
2015-04-23 11:57:27 +02:00
5dc1396eea
Spelling fixes
2015-04-13 11:35:12 -07:00
0ca856d4e8
bugfix #942 : VHDL function bodies in arch declaration not supported
2015-03-31 10:46:24 +02:00
d5ffb55bfd
Corrected ambiguous copyright info.
2015-03-27 18:57:40 +01:00
ab9a8ccbf3
vhdlpp: Added fit_type() & probe_type() for ExpFunc.
2015-03-27 18:57:40 +01:00
e6525ec35f
vhdlpp: Added a constructor for VTypeArray that takes integers as ranges.
2015-03-27 18:57:40 +01:00
afaedbd06d
vhdlpp: Corrected to_integer() & resize() functions.
...
to_integer() handles sign and resize() really applies size casting.
2015-03-27 14:53:43 +01:00
d4237774a5
vhdlpp: Error message for missing types in VTypePrimitive::get_width().
2015-03-27 14:53:43 +01:00
2f2539e557
vhdlpp: Renamed a range_t constructor parameter to be more descriptive.
2015-03-27 14:53:43 +01:00
3b14797075
vhdlpp: Prefix probe for VTypeArray.
2015-03-27 14:53:43 +01:00
d1dc98b7f7
vhdlpp: Changed the workaround for accessing localparam arrays & records.
2015-03-07 20:47:20 +01:00
295e4e7dfb
vhdlpp: Fixed crash on unassociated generics.
2015-03-06 20:39:10 +01:00
807ad8002d
vhdlpp: Check generics when searching through constants.
2015-03-06 20:39:10 +01:00
d3229b9068
vhdlpp: 'string' type is emitted as 'string' instead of 'array <> of character'.
2015-03-06 17:58:04 +01:00
099bb427bc
vhdlpp: ComponentBase::write_to_stream() saves generics.
2015-03-06 17:58:04 +01:00
1de3fb1625
vhdlpp: "resize" function.
2015-03-06 17:58:04 +01:00
e33b8b4dde
vhdlpp: VType::get_width() uses information from Scope to determine the type width.
2015-03-06 17:58:04 +01:00
9128eb67b9
vhdlpp: Evaluates attributes if possible.
2015-03-06 17:32:25 +01:00
afbda099fb
vhdlpp: Workaround to handle constant arrays of vectors & records.
2015-03-06 17:32:25 +01:00
4b0d220671
vhdlpp: get_width() for VType.
2015-03-06 17:32:25 +01:00
a42b056b24
vhdlpp: Alternative way of accessing constant arrays of vectors.
2015-03-06 17:32:25 +01:00
1852c5ab9d
Revert "vhdlpp: Support for accessing words in constant arrays."
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This reverts commit 9ca754b6db
2015-03-06 17:32:25 +01:00
9ca754b6db
vhdlpp: Support for accessing words in constant arrays.
2015-02-19 17:07:41 +01:00
0f0bef32f2
vhdlpp: Architecture elaboration counts errors coming from expression elaboration.
2015-02-19 17:07:41 +01:00
cd55f30a27
vhdlpp: Minor change to ScopeBase::find_constant().
2015-02-19 17:07:41 +01:00
5884879b02
vhdlpp: to_integer() function.
2015-02-19 17:07:41 +01:00
a1a4f47894
vhdlpp: Unnecessary comment.
2015-02-19 17:07:41 +01:00
e569e07d4e
vhdlpp: Type 'NATURAL' is translated to 'int unsigned'.
2015-02-19 17:07:41 +01:00
ee840391d6
vhdlpp: std_logic_vector, signed & unsigned are considered global types.
2015-02-19 17:07:41 +01:00
0046e9eca0
vhdlpp: ActiveScope::is_vector_name() checks also for constants.
2015-02-19 17:07:41 +01:00
f51c037432
vhdlpp: Generics from external packages are accepted (warning instead of error).
2015-02-19 17:07:37 +01:00
763c6fe3c9
vhdlpp: Support for shift operators (SRL, SRR, SRA, SLA).
...
To be done: ROR & ROL.
2015-02-17 10:15:57 +01:00
49b6ddf93c
vhdlpp: Signal/variable assignments can have labels.
2015-02-17 10:15:57 +01:00
12b4914b63
vhdlpp: ExpName resolves enum values.
2015-02-17 10:15:57 +01:00
fc0728ab6f
vhdlpp: Forward typedefs.
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It was required to make it possible to use typedefs in port types.
Types from packages are emitted in `ifdef..`endif instead of package..endpackage.
The purest solution is to keep package..endpackage and emit appropriate prefix.
Also, it would be great to have constants emitted in the same way.
2015-02-17 10:15:57 +01:00
cdf18de10e
vhdlpp: Make integer expressions sized during the emission step.
2015-02-05 16:20:49 +01:00
19ff6a434b
vhdlpp: Alternative way of dealing with unbounded vectors in fuctions (instances).
2015-02-05 12:00:25 +01:00
5349ca9a55
vhdlpp: Added Subprogram::write_to_stream_body() method.
2015-02-05 12:00:25 +01:00
5b7b980ead
vhdlpp: Support for multiple choices in case statements.
2015-02-05 12:00:25 +01:00
a1c2a8e605
vhdlpp: Generic syntax errors display messages.
2015-02-05 11:25:03 +01:00
8777cd8e7c
vhdlpp: Fixed ExpBitstring & ExpRelation write_to_stream() method.
2015-02-05 11:25:03 +01:00
11bb7ac348
vhdlpp: Expression::write_to_stream becomes const.
2015-02-05 11:25:03 +01:00
9de69f2f24
vhdlpp: SequentialStmts write_to_stream() methods.
2015-02-05 11:25:03 +01:00
dae3410dcd
vhdlpp: Variable::write_to_stream().
2015-02-05 11:25:03 +01:00
1a367c84b6
vhdlpp: Subprograms can have instances that take a different set of parameter types.
2015-02-05 11:25:03 +01:00
8a854affa6
vhdlpp: Clone routines for Expression & VType classes.
2015-02-05 11:25:03 +01:00
60077f4f06
vhdlpp: ExpBitstring elaborate_expr().
2015-02-05 11:25:03 +01:00
51ce9f1a60
vhdlpp: Minor correction for casting to integer.
2015-02-05 11:25:03 +01:00
48265ecd9b
vhdlpp: Subprograms return types have their ranges evaluated if possible.
...
Added VTypeArray::evaluate_ranges() method.
2015-02-05 11:24:59 +01:00
abbcea64d0
vhdlpp: Array attributes can be evaluated in packages/functions.
2015-02-04 16:57:43 +01:00
25c3798248
vhdlpp: Elaborate and emit functions work with ScopeBase instead of Architecture.
2015-02-04 16:57:43 +01:00
90293d8e0a
vhdlpp: VTypeArray::is_variable_length() uses ScopeBase to determine if variable has constant length.
2015-02-04 16:57:43 +01:00
621cf37339
vhdlpp: Added ScopeBase::find_param() method.
2015-02-04 16:57:43 +01:00
6d75af86e6
vhdlpp: Added Subprogram::fix_variables() method.
2015-02-04 16:57:43 +01:00
5d26f0e28d
vhdlpp: Added VTypeArray::is_variable_length() method.
2015-02-04 16:57:43 +01:00
774609fbbb
vhdlpp: VTypeArray stores parent type, in case it is a subtype.
2015-02-04 16:57:43 +01:00
9ba7694484
vhdlpp: Minor assert.
2015-02-04 16:57:43 +01:00
870a826225
vhdlpp: Corrected VTypeDef::emit_def() to allow typedefed names in function headers.
2015-02-04 16:57:43 +01:00
2ecfed0baa
vhdlpp: Moved part of check_unb_vector() to fix_logic_darray().
2015-02-04 16:57:43 +01:00
56e410f386
vhdlpp: SigVarBase::peek_name_() method made public.
2015-02-04 16:57:43 +01:00
d4dd635bf6
vhdlpp: Added ExpNew class.
2015-02-04 16:57:43 +01:00
c287281bbe
vhdlpp: Tries to determine if function return type is fixed size.
...
Added Subprogram::fixed_return_type() method.
2015-02-04 16:57:43 +01:00
962330f20a
vhdlpp: Functions support unbounded vectors as return type and parameters.
2015-02-04 16:57:43 +01:00
777e7e0a3d
vhdlpp: Added ExpFunc::func_ret_type() method.
2015-02-04 16:57:43 +01:00
839f9cd7ae
vhdlpp: Added ReturnStmt::cast_to() method.
2015-02-04 16:57:43 +01:00
b8b2f53027
vhdlpp: Added VType::get_generic_typename() method.
2015-02-04 16:57:43 +01:00
9b3bd039bb
vhdlpp: Added ExpCast class.
2015-02-04 16:57:42 +01:00
51b9191021
vhdlpp: Added VType::is_unbounded() method.
2015-02-04 16:57:42 +01:00
ff5b696569
vhdlpp: Improved SequentialStmt visitor.
2015-02-04 16:02:38 +01:00
b05a19dffc
vhdlpp: VTypeArray emits dimensions in a bit smarter way.
2015-02-04 16:02:38 +01:00
e6b22a2bea
vhdlpp: Visitor for SequentialStmt.
2015-02-04 16:02:38 +01:00
0592ba042e
vhdlpp: For-loop emission rewritten to handle 'range in subprograms.
2015-02-04 16:02:38 +01:00
6fd10dedb6
Add some implicit support for std and textio libraries
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Patch submitted by Fabrizio Ferrandi.
2014-12-18 08:20:19 -08:00
2e8c4e3dbc
Basic patch from github #44
2014-11-04 11:39:01 -08:00
c55a013162
vhdlpp: Support for integer() function.
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Note: I could not find any info about the integer() function, but it is
used in the VHDL standard packages (e.g. math_real, see:
http://www.csee.umbc.edu/portal/help/VHDL/packages/mathpack.vhd )
Real numbers are rounded, this is compatible with ModelSim behavior.
2014-10-17 14:53:59 +02:00
dfbca0b186
vhdlpp: Emit use_types in Architecture.
2014-10-17 14:13:06 +02:00
4a779f43bd
vhdlpp: Fix error message for 'right attribute.
2014-10-17 14:13:06 +02:00
97df6183a9
vhdlpp: Emit '-' std_logic value as 'x'.
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Note: It is not a direct ("don't care" vs "unknown"), but I could not
find anything that suits better.
2014-10-17 14:13:06 +02:00
95faed8e9d
vhdlpp: Added basic support for concatenated expressions.
2014-10-15 10:51:21 +02:00
76aab15798
vhdlpp: Minor code cleaning.
2014-10-15 10:51:21 +02:00
e896f0c8e6
Remove some compile warnings in the vhdlpp code
2014-10-14 09:03:42 -07:00
9ff9cbf4aa
vhdlpp: Smarter determining the direction in for loops.
2014-10-10 18:39:14 +02:00
a992f3ce7c
vhdlpp: Evaluation for 'left and 'right attributes.
2014-10-10 18:35:17 +02:00
8cac72192f
vhdlpp: Fix array typedefs in packages.
2014-10-09 10:37:33 +02:00
7f6100be2a
vhdlpp: Emit VHDL 'integer' as SystemVerilog 'int'.
2014-10-09 10:29:14 +02:00
4b60d2737e
vhdlpp: Skip signed & unsigned in types dump in packages.
2014-10-09 10:28:35 +02:00
c7beef907d
vhdlpp: Support for 'range and 'reverse_range attributes.
2014-10-08 11:18:06 +02:00
44da7de651
vhdlpp: prange_t may have the direction determined automatically.
2014-10-08 10:26:37 +02:00
6887c82540
vhdlpp: Added ExpAttribute::write_to_stream().
2014-10-08 10:21:03 +02:00
1333bc54a2
vhdlpp: Support for 'left & 'right attributes.
2014-10-08 10:05:04 +02:00
fddb3ec129
vhdlpp: ForLoopStatement emits range boundaries expressions instead of evaluating them.
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Unfortunately without evaluation it is not possible to warn against
degenerated loops, so it had to be removed.
2014-10-07 14:25:00 +02:00
fde6525acb
vhdlpp: Libraries are searched for subprograms during the ExpFunc elaboration.
2014-10-01 14:56:32 +02:00
194a950f8d
vhdlpp: Elaboration of ExpFunc parameters fallbacks to the types given in the Subprogram header.
2014-09-30 15:59:46 +02:00
9951521212
vhdlpp: Subprogram parameters are taken into account when distinguishing between function calls and vector elements.
2014-09-30 15:59:46 +02:00
9e856810b9
vhdlpp: Workaround to avoid translation of variables to wires in functions.
2014-09-30 15:59:45 +02:00
675b7d8efa
vhdlpp: Support for std_logic_vector return type in functions.
...
VHDL does not allow to specify the size of returned std_logic_vector,
whereas Verilog requires the size to be known in advance. The size of
the vector is determined by checking the type of expression used in the
return statement.
2014-09-30 15:58:26 +02:00
e352bea476
vhdlpp: Support for variable declarations in subprograms.
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Fixes sorrymsg: "variable_declaration not supported."
2014-09-30 15:58:13 +02:00
747e656a0e
vhdlpp: Added ScopeBase::transfer_from() method.
2014-09-30 15:00:55 +02:00
7b5470c8a7
vhdlpp: Subprogram class inherits from ScopeBase.
2014-09-30 15:00:55 +02:00
f5dd2ac87e
vhdlpp: Aggregate expressions for records can be specified in any order.
2014-09-17 16:32:56 +02:00
94abef195a
vhdlpp: Commented out named assignment for records.
2014-09-17 16:30:44 +02:00
54696e0127
vhdlpp: Elaboration & emit support for aggregate initializer expressions in records.
2014-09-17 11:24:16 +02:00
9842035d89
vhdlpp: Simplified the initalization for signals/variables.
2014-09-16 16:31:18 +02:00
e330a0bd6e
vhdlpp: Corrected VTypeArray::write_to_stream().
...
Now it outputs "typedef(range)" instead of "array (range) of type".
2014-09-15 12:10:05 +02:00
cb03802a17
vhdlpp: Added VTypeArray::basic_type() to cope with
...
arrays based on typedefs.
2014-09-15 12:10:05 +02:00
22d18cb28d
vhdlpp: Typedefs in packages are emitted before constants.
2014-09-15 12:10:04 +02:00
c98c3e5d14
vhdlpp: Inlined a few functions.
2014-09-15 12:10:04 +02:00
a63289c2fc
vhdlpp: VTypeArray::range_t handles direction (to/downto).
2014-09-15 12:10:04 +02:00
251b75003f
vhdlpp: Skip writing '=>' for ExpAggregates if there are no fields specified.
2014-09-15 12:10:04 +02:00
01b4d49d4a
vhdlpp: Do not emit constants from packages.
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They are elaborated and emitted by architectures that make use of packages.
2014-09-15 12:10:04 +02:00
f851fc6981
vhdlpp: Fixed ExpAggregate::write_to_stream().
2014-09-15 12:10:04 +02:00
a25cde3bc7
vhdlpp: Added ExpString::write_to_stream().
2014-09-15 12:10:04 +02:00
51b121ae7a
vhdlpp: Added ExpBitString::write_to_stream().
2014-09-15 12:10:04 +02:00
94caa4881e
vhdlpp: Added VTypeEnum::write_to_stream().
2014-09-15 12:10:04 +02:00
ef7ac5ed03
vhdlpp: Elaborate all types of initializing expressions.
2014-09-15 12:10:04 +02:00
684c2fe19e
Fixed enum typedefs.
2014-08-28 11:04:25 +02:00
0f728b9150
vhdlpp: Minor cleaning, fixed copyright notices.
2014-08-25 17:29:35 +02:00
b0c79d5d1c
vhdlpp: Added VType::emit_name() that skips emission of a name if it is empty (otherwise '\' is outputted).
2014-08-25 17:05:15 +02:00
150fe088a6
vhdlpp: VTypeRecord is marked as acceptable in packed arrays. VTypeDef is accepted depending on the base type.
2014-08-25 16:56:46 +02:00
bb66ed8b9d
vhdlpp: "integer" is emitted as "bool[31:0" but is marked as accepted to be used in packed arrays.
2014-08-25 16:51:35 +02:00
b1d15436fd
Removed ExpReal::evaluate().Its signature does not match the one meant to be overridden.
2014-08-22 16:55:47 +02:00
c846b2cf3f
vhdlpp: 'integer' is emitted as 'integer' instead of 'bool [31:0]'.
2014-08-22 16:45:17 +02:00
10446df80e
vhdlpp: Invert range in ExpAggregate when necessary.
2014-08-22 16:23:22 +02:00
0a2100c87f
vhdlpp: Turn on the reg_flag for types that cannot be packed.
2014-08-22 16:22:59 +02:00
27730395ca
vhdlpp: Type of an array is selected depending on the element type.
2014-08-22 10:49:55 +02:00
8e9c25a23e
vhdlpp: Added 'packed' property for VTypes.
...
It detetermines if a type can be used as the base type of a packed array.
2014-08-22 10:45:02 +02:00
72ff9ac00b
vhdlpp: Aggregate expression are elaborated if
...
they are used for Signal/Variable initalization.
2014-08-20 14:18:16 +02:00
c92dea77fc
vhdlpp: Basic support for unbounded array types.
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Once a signal/variable of unbounded array type becomes limited in its size, it
is emitted as a packed array. Therefore currently it works only for
bit/logic/reg/wire types.
2014-08-15 10:21:45 +02:00
9031f392ba
Convert string to bitstring in SigVarBase
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constructor if applicable (vhdlpp).
2014-08-08 11:20:07 +02:00
4786f80b0b
Add the string terminator for binary bitstrings.
2014-08-08 09:52:57 +02:00
d2ad7a4d28
Increase the output precision for floating point types.
2014-08-06 17:04:52 +02:00
5830ecd67e
Avoid freeing the primitive types classes.
2014-08-06 15:01:59 +02:00
69b145e216
Minor cleaning for valgrind output.
2014-08-06 15:01:28 +02:00
5ed60a151f
Added support for real type in vhdlpp.
2014-08-06 15:00:35 +02:00
66d31b02be
Fixed vhdlpp segfault if it processes an entity without any ports declared.
2014-08-04 20:27:21 -07:00
d6b6b76015
Update header files to use a more standard name to prevent rereading
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This is from github report #16 . There are likely a few more issues
that need to be addressed though this takes care of the major ones.
2014-07-23 13:42:56 -07:00
e221a8ced9
Rearrange compiler warning flags
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Before this patch, WARNING_FLAGS applied to both C and C++,
and WARNING_FLAGS_CXX applied to C++ only.
This patch adds a WARNING_FLAGS_CC that applies to C only.
That change should be generally useful; in particular the C
code is almost ready for -Wstrict-prototypes, which does not
apply to C++.
-Wextra (or -W) used to only apply to C++ via WARNING_FLAGS_CXX.
This patch moves it to WARNING_FLAGS, to apply to both C and C++.
Unfortunately, that triggers a ton of warnings.
For now, cover most of the new warnings up by adding
-Wno-unused -Wno-sign-compare -Wno-type-limits
to WARNING_FLAGS_CC. In the long run, I want to change the C coding
style, and take off these disable-warning flags. But those changes
can dribble in as separate commits; this patch is big enough already.
Actually fix a couple missing-field-initializers in libveriuser/veriusertfs.c.
2014-07-09 09:04:17 -07:00
0611135758
Some more cppcheck cleanup/updates
2014-06-29 20:39:40 -07:00
be17bfc0e9
Spelling fixes
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Mostly comments.
One user-visible string ("Evalutated to ") changed in the debug_eval_tree case.
2014-01-30 15:34:20 -08:00
9e25884f12
Fix for br942 - allow function declaration in VHDL architecture.
2013-12-11 23:00:58 +00:00
07cc18284c
Fix print token/argument mismatches and other cppcheck fixes
2013-09-09 13:34:38 -07:00
21b24c7725
Fix more compile warnings and a minor bug
2013-07-11 19:10:25 -07:00
3e75f8e41f
Remove a compile warning
2013-07-11 18:03:00 -07:00
ca9616dc7b
Better simple_expression parse rules.
2013-06-12 14:21:36 -07:00
24bd630cb2
Parse (to sorry messages) unbounded array definitions.
2013-06-12 14:21:36 -07:00
8487cb5616
Do a better job of figuring the vtype of an expression.
2013-06-12 14:21:36 -07:00
d630e4dfe9
Elaborate VHDL entity port types/expressions.
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We need to elaborate expressions so that function calls in
expressions (i.e. ranges) get bound to their proper scope.
This binding is in turn used to emit package scopes. This
is particularly interesting for ports of entities.
2013-06-12 14:21:35 -07:00
3d5765949e
Some shorthand type marks in write_to_stream.
2013-06-12 14:21:35 -07:00
0fcd2d9db6
Handle rising_edge and falling_edge functions.
2013-06-12 14:21:35 -07:00
bc77a19059
Use $ivl_unsigned to implement VHDL to_unsigned function.
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The VHDL to_unsigned function with to arguments is best handled
in the ivl elaborator, so have it generate an $ivlh_to_unsigned
function call in the vhdlpp code, and implement it in the ivl
core.
Also, implement the 'length attribute as a $bits() call for
similar reasons.
2013-06-12 14:09:08 -07:00
dca6171f5f
SV emit function ports in package subprograms.
2013-06-12 14:09:07 -07:00
164b5f9348
Fix SV emit of ForLoopStatement and ReturnStmt.
2013-06-12 14:09:07 -07:00
e927960121
Implement subprogram bodies in package bodies.
2013-06-12 14:09:07 -07:00
6394a4d78d
Rework scope types and constants so we can tell imported from local names.
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The package emit of types and constants needs to know which names are
from the current type and which are imported from libraries. Rework
the scope handling of those names so that the information is preserved.
2013-06-12 14:09:07 -07:00
13be45bd73
Fix dump of primitive CHARACTER types.
2013-06-12 14:09:07 -07:00
7f7decde03
Basic structure for emitting packages.
2013-06-12 14:09:07 -07:00
d9fea802da
Function declarations in packages
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This is still basic. Definitions are still not done.
2013-06-12 14:09:07 -07:00
11682fc7eb
Harmless cleanup of comments / initialization warnings.
2013-04-18 18:18:40 -07:00
d2928d500d
Remove a few more compile error messages from RHEL5
2013-04-17 17:46:05 -07:00
15379f1750
Remove some compile warnings
2013-04-17 17:13:22 -07:00
bad8ed39c1
Parse VHDL subprogram bodies and return statements.
2012-11-03 09:54:07 -07:00
5651e6e001
Improve error handling.
2012-11-02 19:30:12 -07:00
c14134aa2e
Handle genvar variables in expressions.
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In generate for blocks, there is a genvar that can be used in
expressions within the generate block. Generate this genvar in
the generated output, matched to the generate scope.
2012-09-07 15:14:48 -07:00
85e000ed0c
Handle prefix expressions that include array index expressions.
2012-09-03 16:00:10 -07:00
7fad717a1e
Redesign selected_name rule to better handle complex prefixes
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Prefixes of hierarchical names are complex and cannot be handled
by simple strings, to the rules must be reworked.
2012-09-03 16:00:10 -07:00
f5aafc32f9
updated FSF-address
2012-08-29 10:12:10 -07:00
4313fbbf1f
Fix space errors in various files
2012-08-16 11:13:32 -07:00
1749d10966
Fix some clang/bison compile warnings.
2012-08-06 15:49:11 -07:00
befff82655
Spelling fixes
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Comments and debug messages.
2012-07-27 18:25:32 -07:00
621c09105c
Sort the typedef emits so that types are emitted in the order used.
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It is common for typedefs of complex types to use further typedefs.
Emit the type definitions depth first so that the types that are used
are defined first. This reduces the need for pre-declaration of types.
2012-05-22 17:31:27 -07:00
369a0b9eca
VHDL named types work in more places.
2012-05-22 17:31:27 -07:00
4748f0cb5e
Handle incomplete type declarations
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Use these in the package library to allow for arbitrary mixing
of type declaration and use. This makes writing libraries much
easier.
2012-05-22 17:31:27 -07:00
039e6014fe
Rework VType::emit_def methods / use packed arrays to implement arrays.
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VHDL arrays are more like SV packed arrays, so use packed arrays
to implement them.
2012-05-22 17:31:26 -07:00
63b7fe059d
Reword concat to handle aggregate arguments.
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When concatenation expressions have aggregate arguments, we need to
get the type of the result down to the aggregate expressions so that
it can know how to interpret the elements.
2012-05-22 17:31:26 -07:00
67af96fee7
Module output ports use data_type_or_implicit
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This cleans up the parsing of module output ports, allows for more
complex types on the ports, and fixes some bugs.
2012-05-22 17:31:26 -07:00
7e202bb5ca
Fix emit of struct ports/declarations.
2012-05-22 17:31:26 -07:00
71d2401221
Handle VHDL records.
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Elaborate records and emit them as packed SV records. Also handle
record members so handle name prefixes.
While we are at it, handle some cases of array aggregate expressions.
2012-05-22 17:31:26 -07:00
ae06863db1
Elaborate prefix names which may be structure variables.
2012-05-22 17:31:26 -07:00
a5458828cd
Some vhdl parser error handling.
2012-05-22 17:31:26 -07:00
021d944a30
Probe type of ExpName with a record prefix.
2012-05-22 17:31:25 -07:00
7eb89c5548
Parse name prefix syntax for record member reference.
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When signals/variables are records, they are often referenced by
their members, using a prefix.name syntax. Parse that syntax and
generate "sorry" messages in elaboration.
2012-05-22 17:31:25 -07:00
5e7f61ea42
VHDL process sensitivities go to the end of each iteration
2012-05-22 17:31:25 -07:00
9b816f6478
Add support for nested when/else expressions.
2012-05-22 17:31:25 -07:00
1249b5dd32
Initial support for if_generate syntax.
2012-05-22 17:31:25 -07:00
0775e36a67
Properly elaborate argument types for binary relation expressions.
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The argument types of binary relation expressions are decoupled
from the return type for the expression itself.
2012-05-22 17:31:25 -07:00
ed3da959f3
Support types in packages.
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Types declared in packages should be written into the package library.
2012-05-22 17:31:25 -07:00
79435924f2
Move some VType::show methods to ::write_to_stream methods.
2012-05-22 17:31:25 -07:00
9ed56a6354
Parse record types, and some new aggregate types.
2012-05-22 17:31:25 -07:00
84f14dbc81
Spelling fixes to vhdlpp tree
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Mostly comments as usual, but one error message is changed.
2012-05-17 16:42:03 -07:00
9c99bce054
Update lex/yacc builds to be consistent and to support parallel builds
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Not all the lex/yacc (flex/bison) targets were using a consistent syntax.
This patch fixes that and explicitly serializes the *.c/*.cc and *.h build.
Not doing this was causing problem when using make -j. The issue appears to
be that if two targets are specified for a rule (e.g. file.cc file.h: file.y)
make does not realize they are both built by the same call so the rule is
executed twice. Once for the .cc target and once for the .h target. This is
not a problem for a serial build. To work around this only use the .c/.cc
file in the main target and then make the .h file depend on the .c/.cc file
as a sub-target.
2012-01-04 18:21:40 -08:00
aedbda5a75
Identifiers need to be deleted with delete[]
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This patch fixes a mismatch in the delete style.
2011-12-18 16:45:08 -08:00
ed13de131d
Use mkdir() instead of _mkdir() for MinGW
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MinGW-w64 requires the use of mkdir() and MinGW-w32 appears to support
both so use mkdir() to allow compilation to work with both versions.
2011-12-18 11:43:35 -08:00
8df745a281
Remove SV include file and vhdlpp with make uninstall
2011-12-14 18:39:27 -08:00
cc5efa45ba
Fix two bugs and use the more efficient !empty() vs size() > 0
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These two bugs were found with a recent cppcheck addition. It also
changes one occurrence of size() > 0 for the more efficient ! empty().
2011-11-22 19:44:55 -08:00
bcb963a235
Fix Cygwin compile problem (replace abs() call with ?:
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This patch fixes a compile problem in Cygwin where there are two
definitions for abs() that do not match so the C++ code doesn't know
which one to call. To avoid the whole mess replace the call to abs()
with the appropriate ?: construct.
2011-11-17 14:30:33 -08:00
5e4c0c9783
Merge branch 'master' into work9
2011-11-06 10:27:40 -08:00
8e0beff3ab
Handle arrays of vectors in VHDL types.
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This incidentally adds binding of generic to generic instantation.
2011-11-06 09:01:02 -08:00
c1be255844
Fix dump display of array ranges.
2011-11-05 17:22:30 -07:00
cc508d1626
Support write_to_stream for arithmetic expressions.
2011-11-05 15:55:41 -07:00
2063c5ee9d
Support VHDL user defined array types.
2011-11-05 15:55:17 -07:00
58d182bdf3
Compiler fixes for MinGW.
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In MinGW, when parameters are passed to vhdlpp by ivlpp, single quotes
are treated as ordinary characters. Use double quotes instead, as is
done in the driver.
Also, MinGW does not have a standard mkdir() function, so we need to
convert calls to mkdir() into calls to _mkdir().
2011-11-03 19:11:28 -07:00
98d928f6e0
Add support for VHDL for-generate
2011-10-30 17:10:19 -07:00
5724f71339
Elaborate expressions for entity generics.
2011-10-29 17:07:03 -07:00
15da45f7cb
VHDL initialization expressions for signals.
2011-10-29 17:06:40 -07:00
37ef14b1c8
Implement VHDL conf_std_logic_vector() as SystemVerilog size cast.
2011-10-29 14:47:39 -07:00
4f98a6d181
Rewire VHDL addition expression parsing.
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The VHDL LRM addition expression rules are ... different.
2011-10-23 17:31:58 -07:00
2be682f8a5
Support VHDL component instantiations with generics as Verilog parameters.
2011-10-23 17:08:48 -07:00
eeeadea3ac
Fix recently broken write of vhdl packages to work space.
2011-10-16 12:18:34 -07:00
a109df04bb
Proper expression type for vhdl relation expressions.
2011-10-16 11:02:07 -07:00
93e5a72d84
Get parameter output syntax right for vhdlpp.
2011-10-16 11:01:32 -07:00
d9acfe57b1
Put off array bound evaluation / describe entity generics as parameters
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Entity generics are easily implemented as module parameters, so make
it so. Give the parameters their default values from the generic declaration.
Array bounds may use values that cannot be evaluated right away, so
put off their evaluation.
2011-10-15 17:41:48 -07:00
a6f63b8a54
Parse generic clause in entity headers
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The generic clause can create named generics in entities. This patch
gets the parser support for them working, even though they cannot
yet evaluate.
2011-10-15 09:49:24 -07:00
209a78a439
Remove a more cppcheck warnings in vhdlpp.
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This patch removes a few more cppcheck warnings in the vhdlpp directory.
2011-10-14 18:40:39 -07:00
8f17e79b7e
Remove a few cppcheck warnings.
...
This patch removes a few cppcheck warnings.
2011-10-14 18:40:24 -07:00
6268db6e68
Handle simple type declarations.
2011-10-09 15:25:35 -07:00
30cfcbe2dc
Rework elaborate/emit of types.
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This rework is needed to reasonably handle new types, like enums.
2011-10-02 10:56:00 -07:00
271aaf6376
Parse enumeration type declarations.
2011-10-01 17:04:04 -07:00
8003382b3e
Elaborate and emit case statements.
2011-10-01 11:45:28 -07:00
c59d27e19f
Remove more clang warnings.
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clang warns that the yyinput function generated by flex is never used.
2011-09-25 10:14:16 -07:00
eab5bacf9f
Remove clang/clang++ warnings.
...
This patch makes the code consistently use struct/class in the C++ files,
it removes a couple shadow warnings and where a class pointer is passed to
the C routines, it defines the pointer as a class for C++ and as struct for
C and it removes a namespace std duplication.
2011-09-25 10:14:04 -07:00
52019b0e55
Merge branch 'master' into work8
2011-09-18 19:48:50 -07:00
88cce86c63
Emit code for the to_unsigned() bulit-in function.
2011-09-18 19:31:28 -07:00
873a447b5c
Evaluate VHDL <name>'length attribute at compile time.
2011-09-18 17:45:06 -07:00
677a22d353
Generate code for vhdl for loops.
2011-09-18 15:51:31 -07:00
f0e61a1db7
Basic vhdl elaboration for unary not operator.
2011-09-18 15:13:30 -07:00
4d445dc269
Fix parse of unnamed processes.
2011-09-18 09:37:11 -07:00
1d02f89a09
Handle vhdh array aggregate expressions.
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Support the more general case of explicit element expressions
defined at various index positions, mixed with "others" records.
2011-09-11 17:08:22 -07:00
3497e2e663
Distinguish bit selects of entity ports from function calls.
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Besides variables and signals, a name with a bit select may
be an entity port. Distinguish these from function calls.
2011-09-11 15:28:58 -07:00
ca6af1c20d
Fix some space issues.
2011-09-11 11:41:38 -07:00
563d73e7d9
Index/part select of VHDL l-values changes expression type
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The changed expression type impacts how code is generated
for the r-value expression.
2011-09-03 17:57:37 -07:00
6d28c989ce
Handle the basics of aggregate expressions
...
This takes care of the parser support, and a shell of the
elaboration. Handle some special cases all the way through.
2011-09-03 17:11:55 -07:00
Larry Doolittle
Maciej Suminski
Stephen Williams
Cary R
Martin Whitaker
Arun Persaud
Martin Whitaker