 jcirimel
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f590ecf83c
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fix minimum pinv sizing
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2020-04-18 05:51:21 -07:00 |
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jcirimel
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add9ec7b28
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remove excess newlines
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2020-04-18 05:42:23 -07:00 |
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jcirimel
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85bc801689
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fix pinv drc bug
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2020-04-18 05:34:55 -07:00 |
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jcirimel
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1f094b03bc
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use more optimal discrete pinv sizing
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2020-04-18 05:26:39 -07:00 |
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jcirimel
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486819ae0d
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fix width bin typo
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2020-04-17 15:27:36 -07:00 |
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jcirimel
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a158ad1e81
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add missing import
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2020-04-17 14:24:52 -07:00 |
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jcirimel
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9316fb8b01
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Merge branch 'dev' into discrete_models
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2020-04-16 16:48:21 -07:00 |
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jcirimel
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ed54c7ab83
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Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev
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2020-04-16 16:48:07 -07:00 |
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 mrg
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8ece411954
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Merge branch 'dev' into tech_migration
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2020-04-16 11:32:02 -07:00 |
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mrg
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843e9414df
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Parameterize vdd and gnd pin in write driver array.
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2020-04-16 11:28:35 -07:00 |
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mrg
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770533e7b1
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Parameterize vdd and gnd pin in sense amp array.
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2020-04-16 11:27:26 -07:00 |
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mrg
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d1319d633d
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Don't widen too short wires either
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2020-04-16 11:02:54 -07:00 |
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jcirimel
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24e0e326d4
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merge dev in to disc...
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2020-04-16 02:18:39 -07:00 |
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jcirimel
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ebb1a7bedb
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merge local with dev
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2020-04-16 02:16:56 -07:00 |
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mrg
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b347e3f7a8
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Try both layers for reversed layer stacks.
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2020-04-15 16:49:04 -07:00 |
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mrg
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9d2902de9e
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Conditional well spacing
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2020-04-15 15:55:49 -07:00 |
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mrg
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94eb2afa36
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Change to callable DRC rule. Use bottom coordinate for bus offsets.
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2020-04-15 15:29:55 -07:00 |
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mrg
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e95c97d7a5
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PEP8 cleanup
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2020-04-15 14:29:43 -07:00 |
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mrg
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1564d6e02b
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PEP8 cleanup
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2020-04-15 11:24:28 -07:00 |
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mrg
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43fe1ae023
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Improve pitch computation
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2020-04-15 11:16:45 -07:00 |
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mrg
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331a4f4606
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Fix wire width bug in short jogs. PEP8 cleanup.
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2020-04-15 09:48:42 -07:00 |
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jcirimel
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6c1c72c520
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fix pgates binning off-by-one
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2020-04-15 04:09:58 -07:00 |
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mrg
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0941ebc3da
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Fix well spacing issue
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2020-04-14 14:08:07 -07:00 |
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mrg
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32d190b8b1
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Jog connection on M1 for bank select.
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2020-04-14 12:15:56 -07:00 |
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mrg
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43dcf675a1
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Move pnand outputs to M1. Debug hierarchical decoder multirow.
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2020-04-14 10:52:25 -07:00 |
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jcirimel
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5f4ed47c57
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netlist only discrete simulating
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2020-04-13 20:48:34 -07:00 |
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jcirimel
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afcb5174ac
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discrete dff tests working
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2020-04-11 01:19:04 -07:00 |
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mrg
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2e67d44cd7
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First pass of multiple bitcells per decoder row
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2020-04-10 13:29:41 -07:00 |
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jcirimel
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a0eb9839ad
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revert units on sp_lib, begin discrete tx simulation
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2020-04-09 19:39:21 -07:00 |
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mrg
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7888e54fc4
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Remove dynamic bitcell multiple detection.
Check for decoder bitcell multiple in tech file or assume 1.
PEP8 fixes.
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2020-04-09 11:38:18 -07:00 |
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mrg
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8a55c223df
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Use single height for netlist_only mode
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2020-04-09 09:48:54 -07:00 |
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mrg
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58fbc5351a
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Change rows to outputs in hierarchical decoder
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2020-04-08 17:05:16 -07:00 |
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mrg
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745450fadc
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Syntax error
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2020-04-08 17:04:50 -07:00 |
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mrg
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cddfaa0dc8
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Tech dependent fudge factor
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2020-04-08 17:04:14 -07:00 |
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mrg
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ade3b78711
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Add exception errors file
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2020-04-08 16:55:45 -07:00 |
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mrg
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0c27942bb2
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Dynamically try and DRC decoder for height
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2020-04-08 16:45:28 -07:00 |
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 Hunter Nichols
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4103745de2
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Merged with dev, fixed conflict in ptx
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2020-04-08 02:33:05 -07:00 |
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Hunter Nichols
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95363856e4
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Added logical effort and input load for ptx module.
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2020-04-08 02:29:57 -07:00 |
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mrg
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7872b6a68c
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Merge branch 'dev' into tech_migration
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2020-04-07 10:42:05 -07:00 |
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mrg
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a3797094d0
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Swap lvs and sp dimensions for s8
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2020-04-07 10:37:49 -07:00 |
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mrg
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c8c74e8b69
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Fix lvs_write in sram class
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2020-04-06 15:20:59 -07:00 |
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mrg
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f20246abdc
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-04-06 14:08:45 -07:00 |
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mrg
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cd8dc8e20b
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Output lvs model instead of spice model
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2020-04-06 14:08:38 -07:00 |
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mrg
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a12b5d9e6c
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Split decoder pbitcell tests
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2020-04-06 13:31:31 -07:00 |
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 Jesse Cirimelli-Low
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b59c789dec
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remove whitespace
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2020-04-05 03:58:26 -07:00 |
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Jesse Cirimelli-Low
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beef9441b7
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fix pin check debug typo
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2020-04-05 02:55:15 -07:00 |
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Jesse Cirimelli-Low
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8b33cb519f
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Merge branch 'dev' into custom_mod
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2020-04-03 17:05:56 -07:00 |
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mrg
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ab5dd47182
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Ptx is in microns if lvs_lib exists
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2020-04-03 14:06:56 -07:00 |
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mrg
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f358de78bb
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Add optional lvs_lib netlists for LVS usage (sp_lib is for simulation)
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2020-04-03 13:39:54 -07:00 |
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mrg
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8603d3edd6
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PEP8 cleanup
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2020-04-03 11:37:06 -07:00 |
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