mirror of https://github.com/VLSIDA/OpenRAM.git
fix pin check debug typo
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@ -226,7 +226,7 @@ class spice():
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subckt_line = list(filter(subckt.search, self.lvs))[0]
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# parses line into ports and remove subckt
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lvs_pins = subckt_line.split(" ")[2:]
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debug.check(lvs_pins == self.pins, "LVS and spice file pin mismatch.", -1)
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debug.check(lvs_pins == self.pins, "LVS and spice file pin mismatch.")
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def check_net_in_spice(self, net_name):
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"""Checks if a net name exists in the current. Intended to be check nets in hand-made cells."""
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