 mrg
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bc8fd4a882
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Merge branch 'supply_router' into dev
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2021-01-25 11:01:48 -08:00 |
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Matt Guthaus
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eebc2a93b6
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Remove redundant pins when adding each pin
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2021-01-25 09:36:27 -08:00 |
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Matt Guthaus
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30fc81a1f0
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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mrg
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db142bcd5a
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Rename pins to original names
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2021-01-21 15:22:54 -08:00 |
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mrg
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88f2198524
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Always use min area power/IO pins
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2021-01-13 13:56:46 -08:00 |
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mrg
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4991693f1a
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Clean up min area
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2021-01-13 12:32:17 -08:00 |
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mrg
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01d312d65c
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Refactor add power pins
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2021-01-13 10:57:12 -08:00 |
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mrg
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7eb1e2f2d1
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Keep previous pin shapes which were used in router pin connections.
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2021-01-06 11:31:16 -08:00 |
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mrg
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d61fcb3be3
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Fix lpp erase bug in removing router annotations
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2021-01-06 09:39:01 -08:00 |
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mrg
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94b1e729ab
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Don't add vias when placing dff array
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2020-12-22 17:08:53 -08:00 |
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mrg
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286ac635d6
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Escape router changes.
Rename exit router to escape router.
Perform supply and signal escape routing after channel and other routing.
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2020-12-22 16:35:05 -08:00 |
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mrg
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52119fe3b3
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Cleanup exit route. Pins are on perimeter mostly.
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2020-12-22 15:56:51 -08:00 |
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mrg
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ae1c889235
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Updates to IO signal router.
Route signals to perimeter using maze router.
Move IO pins without perimeter pins to M3 using add_io_pin (like add_power_pin).
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2020-12-22 09:39:58 -08:00 |
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mrg
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6101195b51
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Function to remove layout pins.
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2020-12-21 12:44:04 -08:00 |
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mrg
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878a9cee8a
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Add channel routes as flat instances to appease Magic extraction.
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2020-12-15 16:01:39 -08:00 |
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mrg
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fd118c62e5
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Default zom is None not negative.
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2020-12-15 13:27:36 -08:00 |
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mrg
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2954f13294
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Update temp file to be relative
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2020-12-14 14:18:18 -08:00 |
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mrg
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9a3776e758
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Use default zoom for text
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2020-12-14 14:18:00 -08:00 |
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mrg
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d542b7dd76
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Add separate box for pins if it has its own purpose
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2020-12-08 10:31:57 -08:00 |
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mrg
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a2ebaf9f81
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Fix typo
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2020-12-08 10:31:39 -08:00 |
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mrg
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62bf713913
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Only remove files at end of openram
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2020-12-01 11:19:37 -08:00 |
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mrg
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0ccb3487b6
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Set default port map
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2020-11-24 13:27:11 -08:00 |
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mrg
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4e10f6d8a6
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Make cell/bitcell custom cell external accessible.
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2020-11-24 12:01:00 -08:00 |
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mrg
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cdcd115cec
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Fix typos
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2020-11-24 10:35:14 -08:00 |
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 jcirimel
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d2bc7340ed
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finish col cap start row cap
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2020-11-24 03:02:55 -08:00 |
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jcirimel
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f40e5f6dba
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start of adding additional granularity to 1port col caps
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2020-11-23 06:55:47 -08:00 |
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mrg
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5ee3f4cc66
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Many edits.
Use internal vdd/gnd names.
Refactor getters in bitcell to base class.
Add BIAS signal type.
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2020-11-22 08:24:47 -08:00 |
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mrg
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95573c858c
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Can redefine number of ports in custom_cell_properties
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2020-11-21 08:05:49 -08:00 |
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 Hunter Nichols
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53e64fb696
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Merge branch 'dev' into characterizer_bug_fixes
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2020-11-20 11:16:41 -08:00 |
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mrg
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35c162acbd
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Use internal pin names in path names for signal traces.
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2020-11-19 08:45:09 -08:00 |
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mrg
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fbed738b4a
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Merge multiple cell_name fix.
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2020-11-18 16:27:28 -08:00 |
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mrg
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8c72d3f2e7
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PEP8 and small fix
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2020-11-18 14:01:25 -08:00 |
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mrg
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8507881ea8
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Merge branch 's8_single_port' into dev
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2020-11-18 13:59:43 -08:00 |
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jcirimel
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50a0b88ef8
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fix typo
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2020-11-18 11:02:40 -08:00 |
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jcirimel
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520b496611
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check for cell prop names list
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2020-11-18 10:47:05 -08:00 |
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mrg
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305b546ad5
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PEP8 cleanup
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2020-11-17 16:56:00 -08:00 |
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mrg
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02c1fac3b8
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Remove partial Verilog output
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2020-11-17 16:51:08 -08:00 |
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Hunter Nichols
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ac425643a0
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Merge branch 'dev' into characterizer_bug_fixes
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2020-11-17 13:22:56 -08:00 |
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Hunter Nichols
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eaf285639a
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Added debug measurements along main delay paths in SRAM. WIP.
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2020-11-17 12:43:17 -08:00 |
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mrg
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baae28194b
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Add custom cell custom port order code. Update setup/hold to use it.
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2020-11-17 11:12:59 -08:00 |
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mrg
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86799ae3ff
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Small bug fixes related to new name mapping.
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2020-11-16 13:42:42 -08:00 |
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mrg
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1d729e8f02
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Move pin name mapping to layout class.
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2020-11-16 11:04:03 -08:00 |
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mrg
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93e94e26ec
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Get vdd/gnd from properties if it is defined.
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2020-11-16 10:14:37 -08:00 |
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mrg
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e4bc2c4914
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Update property settings with getters/setters
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2020-11-14 08:08:42 -08:00 |
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mrg
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2f994b8c0a
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Change custom cells to use set_ports setter
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2020-11-14 07:15:27 -08:00 |
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mrg
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b4342ac527
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More cleanup
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2020-11-13 17:29:20 -08:00 |
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mrg
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a2b17a271c
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Port type order generated on the fly
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2020-11-13 16:41:02 -08:00 |
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mrg
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01d191da40
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clk_pin is redundant in DFFs
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2020-11-13 16:23:27 -08:00 |
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mrg
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8021430122
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Fix pbitcell erros
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2020-11-13 15:55:55 -08:00 |
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mrg
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c472a94f1e
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Rework bitcells.
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
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2020-11-13 10:07:40 -08:00 |
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