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OpenRAM
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1086 Commits

Author SHA1 Message Date
samuelkcrow 78cabf9ca3 make capped array name more descriptive and add x mode to tests 2023-01-17 10:20:16 -08:00
samuelkcrow f651b484c5 fix capped array tests after dev merge 2022-12-14 08:48:12 -08:00
samuelkcrow 6a8a76dd23 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into no_rbl 2022-12-14 08:13:08 -08:00
Eren Dogan fe81bbfd7e Fix paths in library usage tests 2022-12-02 20:28:14 -08:00
Eren Dogan 6a4f6cbbed Move sram and sram_config to openram namespace 2022-12-02 15:28:06 -08:00
Eren Dogan fe0826d07c Add unit tests for library usage 2022-12-02 13:04:54 -08:00
Eren Dogan b40a17f4a5 Fix log file for sram_compiler tests 2022-12-02 13:00:12 -08:00
Eren Dogan 96e57507bf Add copyright check to code format test 2022-11-30 14:50:43 -08:00
Bugra Onal b9f16ea490 Merge branch 'dev' into char 2022-11-29 14:50:00 -08:00
Eren Dogan a37d41b406 Fix typo 2022-11-27 16:41:28 -08:00
Eren Dogan 316f75861b Fix unit tests running on docker with a hack for now 2022-11-27 14:32:55 -08:00
Eren Dogan fccdc3c45b Use library imports globally 2022-11-27 13:01:20 -08:00
Eren Dogan e718106d87 Change is_unit_test to False by default 2022-11-21 14:52:57 -08:00
Eren Dogan 845f32805f Change compiler name for unit tests 2022-11-06 14:05:08 -08:00
mrg b1a88d8c8a Remove variable reference in ifdef 2022-11-02 08:02:22 -07:00
mrg aeca2c6b88 Allow any definition of KEEP to keep temp files 2022-10-20 14:31:26 -07:00
Bugra Onal 2b79646b8f Merge branch 'dev' into char 2022-10-04 09:09:52 -07:00
samuelkcrow 8bc3903a04 remove end caps from replica column (will not pass sky130 drc) 2022-09-26 14:23:09 -07:00
samuelkcrow 37dee02161 Merge branch 'dev' into no_rbl 2022-09-13 12:34:57 -07:00
samuelkcrow 004ee3748d add option to keep tmp files when running tests with make 2022-09-08 13:40:48 -07:00
samuelkcrow fe0cfac6c8 tests for new capped array module 2022-09-07 12:39:01 -07:00
Bugra Onal 1a214a7309 Fixed utest 25 golden 2022-08-30 09:17:51 -07:00
Bugra Onal 56879bf48b Cleanup 2022-08-18 20:35:34 -07:00
Bugra Onal c0c15537d9 Added golden files for freepdk test 25 2022-08-18 11:04:53 -07:00
Bugra Onal 25cc08db80 Further fixes for new verilog naming convention 2022-08-18 11:03:13 -07:00
Bugra Onal aefe46394c Merge branch 'dev' into multibank 2022-08-12 21:45:26 -07:00
Bugra Onal b33c2ab96c Fixed test 25 golden files 2022-08-12 21:33:40 -07:00
Bugra Onal 623c1ac02f Convert unit test 25 to new modules convert 2022-08-10 16:33:50 -07:00
Bugra Onal c7975e3274 Use fake sram in memchar 2022-08-10 12:22:47 -07:00
Bugra Onal 2101067e4a Characterizer options 2022-08-10 12:22:47 -07:00
samuelkcrow 8872a3e312 add tests 2022-08-10 12:22:47 -07:00
Bugra Onal caac39c88b Added 1bank module check to the multibank test 2022-07-28 15:03:41 -07:00
Bugra Onal 3f1a5a2051 Shrunk address register in multibank verilog 2022-07-28 15:03:41 -07:00
Bugra Onal 6b5fe8a096 Changed test name for multibank verilog test 2022-07-28 15:03:41 -07:00
Bugra Onal 8f00e396cd Added unit test for multibank 2022-07-28 15:03:41 -07:00
Bugra Onal a87b40e1cb Added conditional sections to template 2022-07-28 15:03:41 -07:00
Bugra Onal 9158e92a71 TEmplate rework 2022-07-28 15:03:41 -07:00
Bugra Onal 29079bd6ac Added conditional sections to template 2022-07-28 15:03:41 -07:00
mrg 5db470155e Fix print errors in code format unit test. 2022-07-26 12:20:15 -07:00
samuelkcrow f01e73328d remove superfluous imports from multiport test 2022-07-22 13:12:03 -07:00
samuelkcrow 480862c765 remove sys.path.append calls from tests 2022-07-22 11:24:54 -07:00
Eren Dogan e3fe8c3229 Remove line ending whitespace 2022-07-22 19:52:38 +03:00
Eren Dogan 2a778dca82 Add whitespace check to code format test 2022-07-22 18:22:40 +03:00
Eren Dogan 64c72ee19d Fix typo 2022-07-22 18:15:27 +03:00
Eren Dogan 449c68ccae Fix file setup in code format test 2022-07-22 18:11:14 +03:00
samuelkcrow 75efc476f7 add remaining tests 2022-07-21 19:35:02 -07:00
samuelkcrow 7567db6fe9 add rw port unit test for delay control 2022-07-21 19:35:02 -07:00
Bugra Onal f2cd611cb8 TEmplate rework 2022-07-21 15:45:50 -07:00
mrg d92c7a634d Use packages for imports. 
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
 2022-07-13 15:55:57 -07:00
mrg ac86ad0e8a Move pdk installation inside docker to use Magic from docker image. 2022-06-21 12:10:15 -07:00
mrg e744ffd6ea Move mount to shared target in openram.mk 2022-06-09 06:44:23 -07:00
mrg 9e3a28237f Update port data test for sky130 single port 2022-06-08 17:18:53 -07:00
mrg cb3d7b9d5d Add spares for sky130 unit tests. 2022-05-23 17:27:26 -07:00
mrg f1f4453d14 Add column decoder module with power supply straps. 2022-05-17 13:32:19 -07:00
mrg b1bb9151c4 Reimplement off grid pins. 
Long pins aren't accessed on end pins anymore.
Fix problem with multiple non-enclosed space causing blockages.
Add partial pin offgrid enclosure algorithm.
 2022-05-02 15:43:14 -07:00
mrg 64f2f90664 Rework replica_bitcell_array supplies 
Uses layer and direction preferences in tech file.
Places straps on left/right or top/bottom.
 2022-04-19 08:50:11 -07:00
mrg 23b5655cab Split replica_bitcell_array test 2022-03-23 15:59:29 -07:00
mrg 9f7426052d Split port_address tests 2022-03-23 14:46:41 -07:00
mrg e31bec131c Remove 1rw1r combined test and add separate tests. 2022-03-22 11:59:04 -07:00
mrg 229a3b5b3d By default uniquify instances based on macro name. 2022-03-11 18:01:45 -08:00
mrg 4567c2ebcd Add space after docker command. Regress to klayout v0.27.4 2022-03-10 08:37:48 -08:00
mrg e16defdae4 Add a sleep to see if problem is async one 2022-03-09 10:24:50 -08:00
mrg f17d661e3a Add spare column option to tests for sky130 2022-03-07 07:58:41 -08:00
mrg 4faf97005f Add even columns for sky130 to ring test 2022-03-06 12:21:09 -08:00
mrg 6eeb81b9fe Skip sky130 23_lib tests and 4096 row hierarchical decoder test 2022-03-06 11:27:13 -08:00
mrg a0f1327f5e Add odd rows to 23_lib tests 2022-03-06 11:26:18 -08:00
mrg 6da3e44b6f Split up 06_hierarchical_decoder test 2022-03-06 11:26:03 -08:00
mrg 8c911f70b9 Build changes. 
Don't pull docker since it will be build by CI.
Shuffle tests to stagger technologies and test types.
 2022-03-06 10:31:43 -08:00
mrg 4fac069c3c Skip hspice tests in docker 2022-03-01 14:44:04 -08:00
mrg c12c006799 Add verbose option 2022-03-01 10:50:49 -08:00
mrg 38494458e3 Fix incorrect port 1w to 1r 2022-03-01 10:44:56 -08:00
mrg c223c1ad1c Run docker pull before running all tests for regression 2022-03-01 10:33:40 -08:00
mrg 184888b370 Skip 16 way test for now 2022-02-28 12:03:01 -08:00
mrg 27b4d2edb1 Add 16 way mux SRAM tests 2022-02-28 11:53:24 -08:00
mrg 82c2bc329f Split bank and col mux tests. 2022-02-23 15:39:32 -08:00
mrg 6389d4ac82 Skip all func tests 2022-02-23 15:31:15 -08:00
mrg 1742927751 Split port data tests into individual tests 2022-02-23 11:12:32 -08:00
mrg a75d9fcc76 Fix failing test output of Makefile 2022-02-11 13:11:24 -08:00
mrg a35ab45843 Conditionally set TEST_TECHS. Skip pand4 for sky130. 2022-02-10 11:30:20 -08:00
mrg c471823626 Run individual tests on all technologies by default 2022-02-10 11:18:52 -08:00
mrg 51097b2c8b Revert rm in makefile 2022-02-02 09:38:27 -08:00
mrg 39f1199b63 Always delete result subdir to prevent bad and ok simultaneously 2022-02-02 09:36:19 -08:00
mrg 2d2620d21a Remove dir from bad tests 2022-02-02 07:11:13 -08:00
mrg c75968401c Update for detailed skips. Added some sky130 skips. 2022-02-08 16:04:43 -08:00
mrg 16238af584 Print failing tests before exit 2022-02-08 13:07:37 -08:00
mrg 4d62cbd345 Move pdk paths to docker invocation 2022-02-08 12:05:39 -08:00
mrg b1e1763e14 Fix PDK path for freepdk45 and list FAILED tests explicitly at end. 2022-02-08 11:35:29 -08:00
mrg b641bc8eef Check proper subdir for bad files 2022-02-07 16:30:18 -08:00
mrg a3d3aa514b Add target for all technologies 2022-02-07 11:27:10 -08:00
mrg ee97d87bdf Fix total regress pass or fail check. 2022-02-06 12:36:22 -08:00
mrg 89688de3cf Remove outside of docker space 2022-02-06 09:48:30 -08:00
mrg 93c6565b66 Add total failure of tests 2022-02-06 09:13:36 -08:00
mrg 8653b88206 Remove working temp directories 2022-02-06 09:06:20 -08:00
mrg d716a1c361 Don't stop on fail, archive all results, create .bad file on fail. 2022-02-05 07:50:06 -08:00
mrg e45e2f77c9 Rework regression to use docker. 2022-02-04 17:43:48 -08:00
mrg 049751ae1f FreePDK45 running with klayout and Sky130 running with magic. 2022-02-03 10:19:28 -08:00
mrg 63a6168b35 Merge branch 'dev' into klayout 2022-02-01 11:57:56 -08:00
mrg 06d391b3e3 Keep files during runs in Makefile 2022-01-13 14:41:24 -08:00
mrg 34dd46c918 Exceptions for sky130 spare columns tests 2021-12-17 10:30:43 -08:00
mrg 4fa084f272 Add 1rw decoder test 2021-12-17 10:18:20 -08:00
mrg edf3a701e4 Update options for arguments and readme. 2021-11-16 14:33:35 -08:00
mrg c102ed728c Move tests to test Makefile 2021-11-03 11:36:19 -07:00
mrg e6a009312e Move mem reg before usage for compatibility 2021-10-13 09:46:02 -07:00
mrg 178f1197ca Use spare rows only for sky130 2021-09-07 16:49:11 -07:00
mrg 83f2d14646 Fix unit test errors. 
Skip test 50s for now.
Change golden power values in xyce delay test.
 2021-09-07 14:07:22 -07:00
mrg b2389fe00f Change tolerance to 30% 2021-09-03 14:04:39 -07:00
mrg 90a4ad4d75 Update size of 30 config tests to 2 bits. 2021-07-28 12:05:31 -07:00
mrg 0464ec3f16 Skip 50 tests 2021-07-01 16:38:39 -07:00
mrg 55f09d00a4 Make replica_column sky130 friendly 2021-07-01 16:15:13 -07:00
mrg 879f945aa7 Add risc5 functional tests 2021-07-01 16:13:14 -07:00
mrg 6be24d4c6c Only 25 cycles 2021-07-01 12:50:20 -07:00
mrg 3d2b192682 Add conditional spare row/col to a couple unit tests 2021-07-01 12:49:30 -07:00
mrg 927de3a240 Debugging then disabling spare cols functional sim for now. 2021-06-29 15:47:53 -07:00
mrg c4aec6af8c Functional fixes. 
Off by one error of max address with redundant rows.
Select reads 3x more during functional sim.
 2021-06-29 09:33:44 -07:00
Hunter Nichols 294ccf602e Merged with dev, addressed conflict in port data 2021-06-21 17:23:32 -07:00
mrg 67877175b2 Fix error in no spare column verilog 2021-06-18 08:41:26 -07:00
Jesse Cirimelli-Low 7b7c72706a merge in dev 2021-06-17 09:49:32 -07:00
Jesse Cirimelli-Low 1ce6b4d41a fix freepdk45 2021-06-17 03:21:01 -07:00
Hunter Nichols 131ff8bcef Changed the regression test to only run models for the output being tested. 2021-06-16 23:50:20 -07:00
mrg afe0902547 Enable small short func tests 2021-06-16 19:13:50 -07:00
Hunter Nichols 4132decd32 Merge branch 'dev' into automated_analytical_model 2021-06-14 14:45:48 -07:00
Hunter Nichols 4d22201055 Changed name of regression test since we currently only test the delay. 2021-06-14 10:57:20 -07:00
mrg 53107a8322 Add ring test 2021-06-13 15:03:41 -07:00
Jesse Cirimelli-Low 73cc6b3891 uncomment 4x16 decoder 2021-06-11 18:20:36 -07:00
Hunter Nichols 4ec2e1240f Merge branch 'dev' into automated_analytical_model 2021-06-09 15:45:41 -07:00
Hunter Nichols ccf98ad5a6 Added accuracy check in regression model test. 2021-06-09 13:44:42 -07:00
mrg a1cb20878d Swap LH/HL hold times in sky130. 2021-06-08 11:14:27 -07:00
Hunter Nichols 331e6f8dd5 Added functions for testing accuracy of current regression model and associated test. 2021-06-04 15:04:52 -07:00
Hunter Nichols da67edbde8 Changed input format for delay module in xyce delay test. 2021-05-26 20:11:30 -07:00
Hunter Nichols 2f4f8ca912 Fixed conflicts in delay and elmore modules on merge with dev. 2021-05-25 15:25:43 -07:00
Hunter Nichols 23368c0fcf Updated tests and elmore model with load_slew lists. Changed naming on characterization output to not clash with testing. 2021-05-25 14:49:28 -07:00
mrg d51ec4fe45 Add Xyce tests 2021-05-21 12:04:26 -07:00
mrg d43edd95e4 Update golden tests for verilog 2021-05-06 19:56:22 -07:00
mrg 789a8a1cf0 Update golden verilog results 2021-05-05 15:37:27 -07:00
mrg 5b556e6ef5 Update unit test results with new Verilog models. 2021-04-15 15:48:20 -07:00
mrg b510925bdb Enable pruning by default (except on unit tests) 2021-04-07 16:08:29 -07:00
mrg d609e4ea04 Reimplement trim options (except on unit tests). 
Allow trim netlist to be used for delay and functional simulation.
Each class implements a "trim_insts" set of instances that can be removed.
By default far left, right, top and bottom cells in the bitcell arrays are kept.

Use lvs option in sp_write

Fix lvs option in sram.
 2021-04-07 16:07:56 -07:00
mrg b9086dbbe5 Add unit test times to output. 2021-03-26 06:56:58 -07:00
mrg 4a40e96f6d Control logic route changes. 
Move wl_en to top control signal.
Route wl_en directly to port_address.
Reorder input bus to bank.
 2021-03-24 14:32:10 -07:00
mrg fae72ca993 Test new archive options for github actions. 2021-03-23 13:06:36 -07:00
mrg 7b270514e1 Update multithreaded regression. 
Only do 2 threads for 30 tests.
Don't archive results since they are purged anyways.
16 threads for regression.
Purge temp during regression.
 2021-03-23 10:45:56 -07:00
mrg 671470f5f2 Skywater changes. 
Default 1 thread and no temp subdirectory.
Add skywater setup/hold golden data
Add CLI option for simulation threads (-m)
Add compatibility mode option and nomodcheck for ngspice to speed up sky130 model loading.
Make subdir when using default /tmp dir.
Pass num_threads so temp subdirs are created.
 2021-03-22 15:48:14 -07:00
mrg 4ab694033d Merge remote-tracking branch 'bvhoof/dev' into dev 2021-03-01 12:16:26 -08:00
mrg 7610f23fc7 Sub temp directory. Add github archive. 2021-02-10 15:39:12 -08:00
Bob Vanhoof 3dfc039f6f add technology option passtrough in test 30 2021-02-09 09:32:35 +01:00
mrg b83d93cc9a GitHub Actions CI flow. 2021-02-08 15:46:02 -08:00
mrg e043aaffb3 Don't print DRC/LVS/PEX run stats in regress.py 2021-02-03 15:17:28 -08:00
mrg 19e99d1c7b Enable parallel regression testing. 2021-02-03 14:19:11 -08:00
Hunter Nichols df8d59f32e Merge branch 'dev' into automated_analytical_model 2021-02-01 01:49:45 -08:00
mrg bc8fd4a882 Merge branch 'supply_router' into dev 2021-01-25 11:01:48 -08:00