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Fix incorrect port 1w to 1r

This commit is contained in:
mrg 2022-03-01 10:44:56 -08:00
parent c223c1ad1c
commit 38494458e3
1 changed files with 1 additions and 1 deletions
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2
compiler/tests/Makefile
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@ -38,7 +38,7 @@ BROKEN_STAMPS = \
sky130/19_bank_select_pbitcell_test.ok \
%/19_single_bank_16mux_1rw_1r_test.ok \
%/19_single_bank_16mux_test.ok \
%/20_sram_1bank_16mux_1rw_1w_test.ok \
%/20_sram_1bank_16mux_1rw_1r_test.ok \
%/20_sram_1bank_16mux_test.ok \
%/20_psram_1bank_2mux_1rw_1w_test.ok \
%/20_psram_1bank_2mux_1rw_1w_wmask_test.ok \