mirror of https://github.com/VLSIDA/OpenRAM.git
Change tolerance to 30%
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@ -49,7 +49,7 @@ class model_delay_test(openram_test):
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debug.info(1, "Probe address {0} probe data bit {1}".format(probe_address, probe_data))
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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d = delay(s.s, tempspice, corner)
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m = elmore(s.s, tempspice, corner)
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import tech
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@ -77,9 +77,9 @@ class model_delay_test(openram_test):
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debug.info(1,"Model Delays={}".format(model_delays))
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if OPTS.tech_name == "freepdk45":
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error_tolerance = 0.25
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error_tolerance = 0.30
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elif OPTS.tech_name == "scn4m_subm":
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error_tolerance = 0.25
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error_tolerance = 0.30
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else:
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self.assertTrue(False) # other techs fail
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