mirror of https://github.com/VLSIDA/OpenRAM.git
Use spare rows only for sky130
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parent
83f2d14646
commit
178f1197ca
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@ -26,7 +26,6 @@ class riscv_func_test(openram_test):
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OPTS.netlist_only = True
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OPTS.trim_netlist = False
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if OPTS.tech_name == "sky130":
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num_spare_rows = 1
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num_spare_cols = 1
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@ -16,7 +16,7 @@ from sram_factory import factory
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import debug
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@unittest.skip("SKIPPING 50_riscv_phys_test")
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#@unittest.skip("SKIPPING 50_riscv_phys_test")
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class riscv_phys_test(openram_test):
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def runTest(self):
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@ -24,6 +24,13 @@ class riscv_phys_test(openram_test):
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globals.init_openram(config_file)
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from sram_config import sram_config
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if OPTS.tech_name == "sky130":
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num_spare_rows = 1
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num_spare_cols = 1
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else:
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num_spare_rows = 0
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num_spare_cols = 0
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OPTS.num_rw_ports = 1
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OPTS.num_r_ports = 0
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OPTS.num_w_ports = 0
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@ -36,9 +43,9 @@ class riscv_phys_test(openram_test):
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write_size=8,
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num_words=32,
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num_banks=1,
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num_spare_rows=1,
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num_spare_cols=1)
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c.words_per_row=2
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num_spare_cols=num_spare_cols,
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num_spare_rows=num_spare_rows)
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c.words_per_row=1
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c.recompute_sizes()
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debug.info(1, "Layout test for {}rw,{}r,{}w sram "
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"with {} bit words, {} words, {} words per "
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