By default uniquify instances based on macro name.

compiler/base/hierarchy_design.py

@@ -8,6 +8,7 @@
 import hierarchy_layout
 import hierarchy_spice
 import debug
+import os
 from globals import OPTS
 
 
@@ -22,6 +23,15 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
         self.drc_errors = "skipped"
         self.lvs_errors = "skipped"
 
+        # Flag for library cells which is recomputed in hierachy_layout
+        gds_file = OPTS.openram_tech + "gds_lib/" + cell_name + ".gds"
+        is_library_cell = os.path.isfile(gds_file)
+        # Uniquify names to address the flat GDS namespace
+        # except for the top/output name
+        if not is_library_cell and name != OPTS.output_name:
+            name = OPTS.output_name + "_" + name
+            cell_name = name
+
         hierarchy_spice.spice.__init__(self, name, cell_name)
         hierarchy_layout.layout.__init__(self, name, cell_name)
         self.init_graph_params()

compiler/base/hierarchy_layout.py

@@ -42,6 +42,7 @@ class layout():
         self.cell_name = cell_name
 
         self.gds_file = OPTS.openram_tech + "gds_lib/" + cell_name + ".gds"
+        self.is_library_cell = os.path.isfile(self.gds_file)
 
         self.width = None
         self.height = None
@@ -60,8 +61,6 @@ class layout():
         self.pin_map = {}
         # List of modules we have already visited
         self.visited = []
-        # Flag for library cells
-        self.is_library_cell = False
 
         self.gds_read()
 
@@ -903,10 +902,6 @@ class layout():
         """Reads a GDSII file in the library and checks if it exists
            Otherwise, start a new layout for dynamic generation."""
 
-        # This must be done for netlist only mode too
-        if os.path.isfile(self.gds_file):
-            self.is_library_cell = True
-
         if OPTS.netlist_only:
             self.gds = None
             return

compiler/globals.py

@@ -377,7 +377,6 @@ def read_config(config_file, is_unit_test=True):
                                                          ports,
                                                          OPTS.tech_name)
 
-
 def end_openram():
     """ Clean up openram for a proper exit """
     cleanup_paths()

compiler/openram.py

@@ -74,8 +74,9 @@ for path in output_files:
 
 
 from sram import sram
-s = sram(sram_config=c,
-         name=OPTS.output_name)
+s = sram(name=OPTS.output_name, 
+         sram_config=c)
+         
 
 # Output the files for the resulting SRAM
 s.save()

compiler/options.py

@@ -166,10 +166,6 @@ class options(optparse.Values):
 
     keep_temp = False
 
-    # Add a prefix of the root cell before every structure in the GDS
-    # after outputting the GDS2
-    uniquify = False
-
     # These are the default modules that can be over-riden
     bank_select = "bank_select"
     bitcell_array = "bitcell_array"

compiler/sram/sram.py

@@ -61,26 +61,6 @@ class sram():
     def gds_write(self, name):
         self.s.gds_write(name)
 
-        # This addresses problems with flat GDS namespaces when we
-        # want to merge this SRAM with other SRAMs.
-        if OPTS.uniquify:
-            import gdsMill
-            gds = gdsMill.VlsiLayout()
-            reader = gdsMill.Gds2reader(gds)
-            reader.loadFromFile(name)
-
-            # Uniquify but skip the library cells since they are hard coded
-            try:
-                from tech import library_prefix_name
-            except ImportError:
-                library_prefix_name = None
-            gds.uniquify(library_prefix_name)
-
-            writer = gdsMill.Gds2writer(gds)
-            unique_name = name.replace(".gds", "_unique.gds")
-            writer.writeToFile(unique_name)
-            shutil.move(unique_name, name)
-
     def verilog_write(self, name):
         self.s.verilog_write(name)
 

compiler/tests/configs/config.py

@@ -14,3 +14,4 @@ tech_name = OPTS.tech_name
 nominal_corner_only = True
 check_lvsdrc = True
 
+output_name = "sram"

compiler/tests/configs/config_back_end.py

@@ -15,4 +15,5 @@ nominal_corner_only = True
 check_lvsdrc = True
 spice_name = "ngspice"
 
+output_name = "sram"
 

compiler/tests/configs/config_front_end.py

@@ -11,3 +11,5 @@ num_words = 16
 
 tech_name = OPTS.tech_name
 
+output_name = "sram"
+

technology/freepdk45/tech/freepdk45.lylvs

@@ -214,7 +214,7 @@ connect_global(pwell, "PWELL")
 connect_global(nwell, "NWELL")
 connect_global(bulk, "BULK")
 
-for pat in %w(pinv* pnor* pnand* and?_dec* write_driver* port_address* replica_bitcell_array*)
+for pat in %w(*pinv* *pnor* *pnand* *and?_dec* *write_driver* *port_address* *replica_bitcell_array*)
   connect_explicit(pat, [ "NWELL", "vdd" ])
   connect_explicit(pat, [ "BULK", "PWELL", "gnd" ])
 end