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OpenRAM
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640 Commits

Author SHA1 Message Date
Hunter Nichols a711a5823d Merged dev and fix conflicts in geometry.py 2018-10-24 10:52:22 -07:00
Hunter Nichols 53cb4e7f5e Fixed lib files to be syntactically correct with multiport. Fixed issue in geometry.py that prevented netlist_only option from working. 2018-10-22 23:33:01 -07:00
Hunter Nichols 62439bdac6 Fixed merge conflicts with sram.py 2018-10-22 17:29:14 -07:00
Hunter Nichols 4f08062268 Added custom 1rw+1r bitcell. Testing are currently failing. 2018-10-22 17:02:21 -07:00
Michael Timothy Grimes cda2e93cd7 Adding fix to netlist_only mode in geometry.py. Uncommenting functional tests and running both tests in netlist_only mode. 2018-10-22 09:17:03 -07:00
Matt Guthaus 0aad61892b Supply router working except for off by one rail via error 2018-10-19 14:21:03 -07:00
Matt Guthaus 4bf1e206e2 Merge branch 'dev' into supply_routing 2018-10-17 09:47:18 -07:00
Matt Guthaus e2cfd382b9 Fix print check regression 2018-10-15 13:23:31 -07:00
Michael Timothy Grimes c8c70401ae Redesign of pbitcell for newer process technolgies. 2018-10-15 06:29:51 -07:00
Matt Guthaus ce8c2d983d Update all drc usages to call function type 2018-10-12 14:37:51 -07:00
Matt Guthaus 4932d83afc Add design rules classes for complex design rules 2018-10-12 09:44:36 -07:00
Matt Guthaus 9bb1c2bbcf Fix Future Warning for real 2018-10-10 15:58:16 -07:00
Matt Guthaus fa4dd8881c Fix Future warnings comparison to None 2018-10-10 15:47:14 -07:00
Matt Guthaus 6bbf66d55b Rewrote pin enclosure code to better address off grid pins. 
Include only maximal pin enclosure shapes.
Add smallest area connector for off grid pins.
Fix decoder to use add_power_pin code.
Change permissions.
 2018-10-10 15:15:58 -07:00
Matt Guthaus a2b1d025ab Merge multiport 2018-10-08 11:45:50 -07:00
Matt Guthaus 3244e01ca1 Add copy power pin function 2018-10-08 09:56:39 -07:00
Michael Timothy Grimes 6ef1a3c755 Improvements to functional test. Now will read or write in a random sequence, using randomly generated words and addresses, and using random ports in the multiported cases. Functional test still has some bugs that are being worked out so it will sometimes fail and sometimes not fail. 2018-10-08 06:34:36 -07:00
Matt Guthaus 8499983cc2 Add supply router to top-level SRAM. Change get_pins to elegantly fail. 2018-10-06 08:30:38 -07:00
Matt Guthaus 985d04d4b5 Cleanup of router. 
Made offsets in geometry snap to grid.
Changed gds_write to use list for visited flag.
Rewrite self.gds each call in case of any changes.
 2018-10-04 14:04:29 -07:00
Michael Timothy Grimes 34d8a19871 Adding simulation.py for common functions between functional and delay tests. Updating functional test. 2018-10-04 09:29:44 -07:00
Michael Timothy Grimes a71486e22f Adding mutliport constants to design.py to reduce the need for copied code across multiple modules. 2018-09-28 00:11:39 -07:00
Matt Guthaus 9b0142d6b9 Comment debug for possible performance issue 2018-09-24 11:44:32 -07:00
Matt Guthaus 87502374c5 DRC clean supply grid routing on control logic. 2018-09-20 16:00:13 -07:00
Matt Guthaus fd9ffe30d6 Add layer width options to route object 
Modify router to use track-width routes.
 2018-09-18 15:12:53 -07:00
Matt Guthaus 8d2804b9cb Supply router working except: 
Off grid pins. Some pins do now span enough of the routing track and must be patched.
  Route track width. Instead of minimum width route, it should be the track width.
 2018-09-18 12:57:39 -07:00
Matt Guthaus 60cceab50a Merge branch 'dev' into supply_routing 2018-09-17 11:34:31 -07:00
Matt Guthaus a3c2b4384a Improve comments. Simplify function interface for channel route. 2018-09-11 15:53:12 -07:00
Matt Guthaus 3587f90e94 Fix copy pasta error in create vertical channel route 2018-09-11 14:47:55 -07:00
Matt Guthaus 5e34233479 Finish new VCG testing. 
Reversed VCG graph edge directions.
Channel tracks get added left to right or top down like
normal left edge algorithm examples.
 2018-09-11 14:24:13 -07:00
Matt Guthaus fcc4a75295 Create VCG using nets as nodes rather than pins. 2018-09-11 13:28:28 -07:00
Matt Guthaus 69261a0dc1 Routing and connecting rails with vias done. 
Refactored grid path class.
Added direction enum.
Does not route multi-track width wires in signal router.
 2018-09-07 14:46:58 -07:00
Matt Guthaus c2c17a33d2 Horizontal and vertical grid wires done. 2018-09-06 14:30:59 -07:00
Matt Guthaus cd987479b8 Updates to supply routing. 
Rename astar_grid to signal_grid to parallel supply routing.
Wave expansion for supply rails.
Pin addition for supply rails.
 2018-09-06 11:54:14 -07:00
Matt Guthaus b1c63a6c62 Add inflate blockages and remove pins from blockages. 2018-09-05 11:06:17 -07:00
Matt Guthaus 0f87ba742f Add back LEF blockages. Remove "absolute" flags from GDS output 2018-09-05 09:28:43 -07:00
Matt Guthaus 8ffdcdf277 Fixed bit shift amount error. Removed rotate flag for Calibre. 2018-09-04 17:27:50 -07:00
Matt Guthaus 5395f21be9 Remove unique id in contact that was used for debugging 2018-09-04 16:40:52 -07:00
Matt Guthaus 9d40cd4a03 Remove verbose print statement in add_power_pin 2018-09-04 16:39:13 -07:00
Matt Guthaus 378993ca22 Found rotate bug in transformCoordinate. Cleaned up transFlags. 2018-09-04 16:35:40 -07:00
Matt Guthaus 73289a6090 Clean up GdsMill. Fix rotate bug I introduced in transFlags! 2018-08-29 15:34:45 -07:00
Matt Guthaus 27bb1d2ee7 Rewrite blockage routines in router. Clean up GdsMill code. 2018-08-29 15:34:45 -07:00
Matt Guthaus 6220ea6d47 Update router to work with pin_layout structure. 2018-08-29 15:34:45 -07:00
Matt Guthaus e17c69be3e Clean up new code for add_modules, add_pins and netlist/layouts. 2018-08-28 10:24:09 -07:00
Matt Guthaus 6401cbf2a6 Move place function to instance class rather than hierarchy. 2018-08-27 17:25:39 -07:00
Matt Guthaus 8664f7a0b8 Converted all modules to not run create_layout when netlist_only 
mode is enabled.
 2018-08-27 16:42:48 -07:00
Matt Guthaus 0daad338e4 All modules have split netlist/layout. 2018-08-27 11:13:34 -07:00
Matt Guthaus 138a70fc23 Add place_inst routine. 
Separate create netlist and layout in some modules.
 2018-08-27 10:42:40 -07:00
Matt Guthaus e3f2ee8a7e Fix VCG error in channel route. 
Note, the channel routing algorithm still does not handle
horizontal conflicts or cyclic vertical conflicts!
 2018-08-15 14:19:04 -07:00
Matt Guthaus 34736b7b3f Remove carriage returns form python files 2018-08-07 09:44:01 -07:00
Matt Guthaus c0d5f781cf Not sure how VCG channel constraint got removed. Fixed this bug before... 2018-07-27 15:15:40 -07:00
Matt Guthaus dd7069dd98 Remove print statement 2018-07-25 15:51:48 -07:00
Matt Guthaus d6df215718 Always use m2_pitch as default for channel for via spacing rules 2018-07-25 15:47:11 -07:00
Matt Guthaus 6d71c3f790 Fix bug to remove pin from conflicts in addition to graph keys 2018-07-25 15:36:16 -07:00
Matt Guthaus 7c254d540d Change channel route api to use pin maps instead of an insteads for cases where there are multiple instances that have the pins (e.g. decoders) 2018-07-25 11:37:06 -07:00
Matt Guthaus f7a2766c29 First draft of naive channel route in hierarchy_layout. It doesn't implement horizontal conflicts or try to minimize the number of channels. 2018-07-25 11:13:30 -07:00
Matt Guthaus 48d3b25b74 Rotate the output pins of the control logic. Need to fix this permanently. 2018-07-24 14:26:01 -07:00
Matt Guthaus 45a53ed089 Rotate via in center for freepdk 2018-07-19 14:01:48 -07:00
Matt Guthaus 51958814a0 Fixing power via problems in freepdk45 2018-07-19 10:23:08 -07:00
Matt Guthaus e82f97cce1 Add create_bus and connect_bus api 2018-07-17 14:23:29 -07:00
Matt Guthaus ac22b1145f Convert bank to use create_bus routines. 
Modify control logic to have correct offset in SRAM.
 2018-07-16 14:13:41 -07:00
Matt Guthaus 77e786ae5e Fix bug in recomputing boundary with a new offset 2018-07-16 13:46:12 -07:00
Matt Guthaus 3bbb604504 Add new power supplies to delay chain 2018-07-16 10:19:52 -07:00
Matt Guthaus f3ae29fe0b Getting single bank to work reliably. Removed tri_gate from bank 
for now. Will add it in multibank arrays only. Not needed for
separate DIN and DOUT ports.
 2018-07-13 14:45:46 -07:00
Matt Guthaus c6503dd771 Modify unit tests to reset options during init_openram so 
that they don't use old parameters after a failure.
 2018-07-10 16:39:32 -07:00
Matt Guthaus d95a1925d4 Refactor banked SRAM into multiple files and dynamically load in SRAM 2018-07-10 14:17:09 -07:00
Matt Guthaus f5855ee68a Fix analytical power of contact with new hierarchy_design level introduced. 2018-07-10 10:17:23 -07:00
Matt Guthaus 25cf57ede5 Push create bus functions down into layout class. 2018-07-10 10:06:59 -07:00
Matt Guthaus 9d5e5086a1 Add new extra design class with additional hierarchy for shared design rules 2018-07-09 15:43:26 -07:00
Matt Guthaus 94db2052dd Consolidate metal pitch rules to new design class 2018-07-09 15:42:46 -07:00
Matt Guthaus 2833b706c7 Fix duplicate name check for some modules by checking if name is a substring. Allows pbitcell to pass. 2018-06-29 09:23:23 -07:00
Matt Guthaus f34c4eb7dc Convert entire OpenRAM to use python3. Works with Python 3.6. 
Major changes:
Remove mpmath library and use numpy instead.
Convert bytes to new bytearrays.
Fix class name check for duplicate gds instances.
Add explicit integer conversion from floats.
Fix importlib reload from importlib library
Fix new key/index syntax issues.
Fix filter and map conversion to lists.
Fix deprecation warnings.
Fix Circuits vs Netlist in Magic LVS results.
Fix file closing warnings.
 2018-05-14 16:15:45 -07:00
Matt Guthaus 97c08bce95 Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control. 
Shift s_en buffers even with other cells.
 2018-03-23 08:14:09 -07:00
Matt Guthaus 5bf915a232 Detect via size for power ring. 2018-03-23 08:13:28 -07:00
Matt Guthaus ed2fa10caa Use LSB for column mux. 
Detect via size for power ring.
 2018-03-23 08:13:20 -07:00
Matt Guthaus bab92fcf38 Rework hierarchical decoder to not be folded. Remove address from central bank bus and access via side pins now. Eight way column mux now works. 2018-03-23 08:13:20 -07:00
Matt Guthaus 1f81b24e96 Single bank passing DRC and LVS again. 
Unfold hierarchical decoder to improve routability.
 2018-03-23 08:13:10 -07:00
Matt Guthaus b867e163a6 Move label pins to center like layout pins. 
Rework of control logic with vertical poly. Passes DRC/LVS.
Single bank passing DRC.
 2018-03-23 08:12:59 -07:00
Matt Guthaus ed8eaed54f Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array. 2018-03-23 08:12:47 -07:00
Matt Guthaus 242a1a68e0 Fix duplicate instance gds output bug that only showed up in Magic extraction. Every time we saved a GDS, additional instances were put in the GDS file. Most extraction tools ignored this, but Magic actually extracted duplicates. 2018-03-02 18:05:46 -08:00
Matt Guthaus 7293eb33bc Merge branch 'dev' of https://github.com/mguthaus/OpenRAM into dev 2018-03-02 10:30:16 -08:00
Matt Guthaus 2b839d34a3 Get rid of netgen error of undefined dlatch. Fix sp_read to find correct subckt name and pins. 2018-02-27 08:59:46 -08:00
Hunter Nichols d0e6dc9ce7 First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
Hunter Nichols 62ad30e741 Added initial version of analytical power esitmation. Loops through instances but power estimate is not accurate. 2018-02-22 19:35:54 -08:00
Hunter Nichols beb7dad9bc Added corner paramters to power functions. This commit does not compile (sorry) 2018-02-22 00:15:55 -08:00
Hunter Nichols d4a0f48d4f Added power calculations for inverter. Still testing. 2018-02-21 19:51:21 -08:00
Hunter Nichols 179a27b0e3 Added some power functions. 2018-02-20 18:22:23 -08:00
Matt Guthaus d19867e64c Move utils to base. 2018-02-09 10:42:23 -08:00
Matt Guthaus 84c798d9e4 Move last few modules to base dir 2018-02-09 10:29:37 -08:00
Matt Guthaus 15747b4759 Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev 2018-02-09 10:25:28 -08:00
Matt Guthaus 7100d6f904 Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00