 mrg
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bdda7c4f5f
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Add bl/br pins to dummy array
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2020-11-12 12:38:09 -08:00 |
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mrg
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8be1436d51
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Use OPTS.bitcell everywhere
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2020-11-05 16:55:08 -08:00 |
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mrg
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1890385be1
|
Use custom cells when needed.
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2020-11-03 11:58:25 -08:00 |
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mrg
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cb3e9517bb
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Use cell_properties to override cell names
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2020-11-03 07:06:01 -08:00 |
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mrg
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da721a677d
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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mrg
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fa89b73ef8
|
PR from mithro + other changable GDS file names
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2020-11-02 16:00:16 -08:00 |
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mrg
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857f5cb136
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Fix copy pasta: decoder to predecode
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2020-10-28 15:46:10 -07:00 |
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mrg
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00cb8a28d9
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Fix supply layer query
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2020-10-28 10:36:13 -07:00 |
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mrg
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acfec369d6
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Add ptx cell properties
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2020-10-28 09:54:15 -07:00 |
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mrg
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25495f3d94
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getattr for bank parameters
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2020-10-28 09:21:36 -07:00 |
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mrg
|
611a4155b9
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Add initial custom layer properties.
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2020-10-27 15:11:04 -07:00 |
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mrg
|
dc991cbcab
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Use pin of pgate to figure out supply layer.
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2020-10-26 15:54:16 -07:00 |
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mrg
|
38ba5fc10d
|
Use pin of pgate to figure out supply layer.
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2020-10-26 15:53:22 -07:00 |
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mrg
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804814d18d
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Add bitlines to dummy modules
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2020-10-16 13:43:56 -07:00 |
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mrg
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20be7caf98
|
Make conditional wl and bl for dummy rows/cols.
|
2020-10-15 13:56:37 -07:00 |
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mrg
|
6a1f12b62d
|
Refactored to utilize OOP
|
2020-10-13 11:07:31 -07:00 |
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mrg
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68d74737f7
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Different bitcell and array supply pins
|
2020-10-13 07:41:21 -07:00 |
|
 jcirimel
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05667d784f
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move sky130 specific stuff to tech module lib
|
2020-10-13 04:48:10 -07:00 |
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mrg
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c3d6be27be
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Fix argument name bug for remove wordlines
|
2020-10-08 16:58:38 -07:00 |
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mrg
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8d5db50062
|
Fix missing update for left RBL offset
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2020-10-08 16:40:53 -07:00 |
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mrg
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b0b15e8151
|
Fix indent bug that failed to create rbl wl pin labels.
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2020-10-08 15:28:01 -07:00 |
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mrg
|
01fe02bd90
|
Fixes to replica bitline array.
Copy pasta error for right dummy column offset.
Put end_caps in try/except block.
PEP 8 formatting
|
2020-10-08 14:53:44 -07:00 |
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|
jcirimel
|
1e7ae06b7e
|
fix extra wl in col end, work on bring wl pins out to row end array, TODO: mirror alternating row end
|
2020-10-08 05:32:03 -07:00 |
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jcirimel
|
d40c3588ed
|
no wl for col end
|
2020-10-08 03:34:16 -07:00 |
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|
jcirimel
|
4a1a7e637e
|
merge in dev
|
2020-10-07 11:54:07 -07:00 |
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mrg
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483f6b187c
|
RBL driver supply location differs for sky130 and other techs
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2020-10-06 16:47:32 -07:00 |
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mrg
|
c2629edc1b
|
Allow 16-way column mux
|
2020-10-06 16:27:02 -07:00 |
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|
jcirimel
|
13e2a9f5f7
|
fix missed self.left_rbl refactor
|
2020-10-06 05:11:15 -07:00 |
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|
jcirimel
|
888646cdf9
|
merge in wlbuf and begin work on 32kb memory
|
2020-10-06 05:03:59 -07:00 |
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|
mrg
|
da83824a70
|
Merge branch 'wlbuffer' into dev
|
2020-10-05 15:33:54 -07:00 |
|
|
mrg
|
4a58f09c1c
|
Use 4x16 decoder with dual port bitcell in tests.
|
2020-10-05 10:52:56 -07:00 |
|
|
mrg
|
c06b02e6fc
|
Rename single_level_column_mux to just column_mux
|
2020-10-05 08:56:51 -07:00 |
|
|
mrg
|
f8146e3f69
|
Add decoder4x16
|
2020-10-02 15:52:09 -07:00 |
|
|
mrg
|
8ce23d7f17
|
Provide unique WL driver instance name
|
2020-10-01 07:17:32 -07:00 |
|
|
Matt Guthaus
|
112d57d90a
|
Enable riscv tests
|
2020-09-30 12:39:40 -07:00 |
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|
mrg
|
f4e6a8895b
|
Update riscv unit test
|
2020-09-30 08:50:58 -07:00 |
|
|
jcirimel
|
7cbf456a4f
|
sky130 rba done
|
2020-09-30 07:34:05 -07:00 |
|
|
mrg
|
b147e8485c
|
PEP8 formatting
|
2020-09-29 16:52:27 -07:00 |
|
|
mrg
|
066570bfeb
|
Fix length of write driver
|
2020-09-29 16:51:55 -07:00 |
|
|
mrg
|
449a4c2660
|
Exclude bitcells in other local areas not of interest
|
2020-09-29 12:15:42 -07:00 |
|
|
mrg
|
d7e2340e62
|
Lots of PEP8 cleanup. Refactor path graph to simulation class.
|
2020-09-29 10:26:31 -07:00 |
|
|
mrg
|
b2dab486fc
|
Add draft of path exclusion calls
|
2020-09-28 16:05:21 -07:00 |
|
|
mrg
|
4a987bef9a
|
Merge branch 'wlbuffer' into dev
|
2020-09-28 15:51:45 -07:00 |
|
|
mrg
|
159c04a25d
|
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
|
2020-09-28 15:51:35 -07:00 |
|
|
mrg
|
70c90ca7fb
|
Replica bitcell array bbox to include unused WL gnd pins.
|
2020-09-28 14:49:33 -07:00 |
|
|
mrg
|
9c6d8d7aed
|
Zjob to bottom.
|
2020-09-28 13:16:03 -07:00 |
|
|
mrg
|
5ab0d01779
|
Remove zjog and go with L shape.
|
2020-09-28 12:48:37 -07:00 |
|
|
mrg
|
d65eb16513
|
Zjog the WL enable. Min driver is 1.
|
2020-09-28 12:24:55 -07:00 |
|
|
mrg
|
6f06bb9dd5
|
Create sized RBL WL driver in port_address
|
2020-09-28 11:30:21 -07:00 |
|
|
mrg
|
88731ccd8e
|
Fix rounding error for wmask with various word_size
|
2020-09-28 09:53:01 -07:00 |
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