 Hunter Nichols
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ce9036af76
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Moved model scripts to characterizer dir
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2020-12-02 13:25:03 -08:00 |
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Hunter Nichols
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acf8e46b55
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Fixed import of utility scripts for model generation
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2020-11-20 13:43:36 -08:00 |
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Hunter Nichols
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1143dbec94
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Added initial scripts and data to generate analytical model
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2020-11-20 12:40:04 -08:00 |
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 mrg
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b77f168270
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Fix original pin name bug in bitcell too.
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2020-11-19 15:12:02 -08:00 |
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mrg
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033111a5f3
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Default to no hierarchical word lines.
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2020-11-19 10:48:35 -08:00 |
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mrg
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35c162acbd
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Use internal pin names in path names for signal traces.
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2020-11-19 08:45:09 -08:00 |
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mrg
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fbed738b4a
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Merge multiple cell_name fix.
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2020-11-18 16:27:28 -08:00 |
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mrg
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8c72d3f2e7
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PEP8 and small fix
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2020-11-18 14:01:25 -08:00 |
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mrg
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8507881ea8
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Merge branch 's8_single_port' into dev
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2020-11-18 13:59:43 -08:00 |
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 jcirimel
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50a0b88ef8
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fix typo
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2020-11-18 11:02:40 -08:00 |
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jcirimel
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520b496611
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check for cell prop names list
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2020-11-18 10:47:05 -08:00 |
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mrg
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6cfa20731c
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Consistent naming in example configs
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2020-11-18 09:59:38 -08:00 |
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mrg
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305b546ad5
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PEP8 cleanup
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2020-11-17 16:56:00 -08:00 |
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mrg
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02c1fac3b8
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Remove partial Verilog output
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2020-11-17 16:51:08 -08:00 |
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mrg
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baae28194b
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Add custom cell custom port order code. Update setup/hold to use it.
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2020-11-17 11:12:59 -08:00 |
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mrg
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80333ffacb
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Fix setup/hold characterization to use custom cell and pin names/orders.
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2020-11-17 09:44:03 -08:00 |
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jcirimel
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825375d76d
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Merge branch 'dev' into s8_single_port
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2020-11-17 04:41:19 -08:00 |
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mrg
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902b92223f
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Small fix for finding pin names in timing graph.
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2020-11-16 13:57:31 -08:00 |
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mrg
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86799ae3ff
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Small bug fixes related to new name mapping.
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2020-11-16 13:42:42 -08:00 |
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mrg
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1d729e8f02
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Move pin name mapping to layout class.
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2020-11-16 11:04:03 -08:00 |
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mrg
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93e94e26ec
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Get vdd/gnd from properties if it is defined.
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2020-11-16 10:14:37 -08:00 |
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mrg
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7512aa6e70
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Skip test 50 which is too slow
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2020-11-16 08:59:25 -08:00 |
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mrg
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e4bc2c4914
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Update property settings with getters/setters
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2020-11-14 08:08:42 -08:00 |
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mrg
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2f994b8c0a
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Change custom cells to use set_ports setter
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2020-11-14 07:15:27 -08:00 |
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mrg
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1624d50ca9
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Fix props bug again.
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2020-11-13 20:35:19 -08:00 |
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mrg
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e9420d57c2
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Fix missing attributes
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2020-11-13 19:04:26 -08:00 |
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mrg
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b4342ac527
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More cleanup
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2020-11-13 17:29:20 -08:00 |
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mrg
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a2b17a271c
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Port type order generated on the fly
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2020-11-13 16:41:02 -08:00 |
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mrg
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01d191da40
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clk_pin is redundant in DFFs
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2020-11-13 16:23:27 -08:00 |
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mrg
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620e271562
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Fix various typos and errors
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2020-11-13 16:04:07 -08:00 |
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mrg
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8021430122
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Fix pbitcell erros
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2020-11-13 15:55:55 -08:00 |
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mrg
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c472a94f1e
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Rework bitcells.
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
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2020-11-13 10:07:40 -08:00 |
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mrg
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3567a3e913
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Remove 1rw_1r
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2020-11-13 08:10:16 -08:00 |
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mrg
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cf63499e76
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Convert bitcells to 1port and 2port
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2020-11-13 08:09:21 -08:00 |
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mrg
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198c0faf85
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Remove special s8 6t names
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2020-11-13 07:45:31 -08:00 |
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mrg
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662d4ea724
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Merge remote-tracking branch 'private/drclvs' into dev
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2020-11-12 16:01:07 -08:00 |
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mrg
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e6a7ecae84
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Fix missing default path in pex
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2020-11-12 14:43:57 -08:00 |
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mrg
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9eeab14639
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Add comment before pininfo
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2020-11-12 14:33:42 -08:00 |
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mrg
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bdda7c4f5f
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Add bl/br pins to dummy array
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2020-11-12 12:38:09 -08:00 |
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mrg
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190234df58
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Add PININFO to outputs too
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2020-11-12 12:12:53 -08:00 |
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mrg
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63941a10e1
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Add None as sp_file parameter to local_drc_check
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2020-11-12 10:01:38 -08:00 |
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mrg
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a2f29e5edd
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Fix missing nand4_leakage #97
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2020-11-12 09:48:08 -08:00 |
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mrg
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d4c4658c77
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Clean up invalid routing layer error message
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2020-11-12 09:43:08 -08:00 |
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mrg
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d3cb22c8c1
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Fix pin vs module names issue #26
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2020-11-12 09:33:48 -08:00 |
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mrg
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537e862d48
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Add -full to LVS script
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2020-11-10 20:38:41 -08:00 |
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mrg
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03dad01e4c
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Use readspice to define ports from sp netlist in Magic extract.
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2020-11-10 17:06:24 -08:00 |
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mrg
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31ae56ff39
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Simplify to a single DRC/LVS library test.
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2020-11-10 16:45:00 -08:00 |
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mrg
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56c2222c2b
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Temp comment Magic GDS filter code.
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2020-11-10 13:37:18 -08:00 |
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jcirimel
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5e2c199d38
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Merge branch 'dev' into s8_single_port
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2020-11-10 03:15:44 -08:00 |
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mrg
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57e708a6e1
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Add 200 cycles. Can be commented out or run for shorter.
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2020-11-09 15:20:36 -08:00 |
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