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OpenRAM
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3,070 Commits 4 Branches 63 Tags 78 MiB
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816 Commits

Author SHA1 Message Date
mrg 7512aa6e70 Skip test 50 which is too slow 2020-11-16 08:59:25 -08:00
mrg 2f994b8c0a Change custom cells to use set_ports setter 2020-11-14 07:15:27 -08:00
mrg 63941a10e1 Add None as sp_file parameter to local_drc_check 2020-11-12 10:01:38 -08:00
mrg 03dad01e4c Use readspice to define ports from sp netlist in Magic extract. 2020-11-10 17:06:24 -08:00
mrg 31ae56ff39 Simplify to a single DRC/LVS library test. 2020-11-10 16:45:00 -08:00
mrg 2c203530ad Merge branch 'drclvs' into dev 2020-11-09 14:36:36 -08:00
mrg 0ba2feee53 Fix errors in new run_sim calls and corners 2020-11-09 13:59:46 -08:00
mrg 532492d5ae Output functional stimulus to output directory. 2020-11-09 12:00:25 -08:00
mrg 31d21e169f Skip LEF test as correct output keeps changing. 2020-11-09 11:14:55 -08:00
mrg 66633a843b Add PDK layer names to tech file 2020-11-09 09:10:43 -08:00
mrg 2da9c307db Disable 4x16 decoder test for now 2020-11-06 13:50:04 -08:00
mrg 147649e142 Why was single port decoder test a dual port? 2020-11-06 12:21:30 -08:00
mrg 2c76a2680f Adjust openram options. 
Remove option -d (dontpurge) and replace with keeptemp
Add option -d (debug) to drop into pdb.
Add option -k (--keeptemp) to keep temp files
 2020-11-05 13:12:26 -08:00
mrg fb0b285652 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-11-04 10:40:20 -08:00
mrg 6e12d4d46c Skip tri gate array test 2020-11-04 06:57:51 -08:00
mrg 29ac541b28 Refactor dynamic cell name to utilize base class 2020-11-03 13:18:46 -08:00
mrg 87419bd640 Fix bitcell and pbitcell with different cell names 2020-11-03 11:30:40 -08:00
mrg cb3e9517bb Use cell_properties to override cell names 2020-11-03 07:06:01 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg 8c4584daa1 Missing import fix. 2020-11-03 06:09:42 -08:00
mrg f9787eb878 Use bitcell_base for all bitcells. Fix missing setup_bitcell call 2020-11-02 17:00:15 -08:00
mrg fa89b73ef8 PR from mithro + other changable GDS file names 2020-11-02 16:00:16 -08:00
mrg cbf9c48504 Names in skiptests changed. Reduce grid router verbosity. 2020-10-23 09:22:59 -07:00
mrg 43d2058b3c Remove temp files 2020-10-08 10:35:27 -07:00
mrg 9a0fc8047b Remove diff 2020-10-08 09:53:52 -07:00
mrg 7076c376e0 Remove log from branch 2020-10-08 09:53:17 -07:00
jcirimel 1e7ae06b7e fix extra wl in col end, work on bring wl pins out to row end array, TODO: mirror alternating row end 2020-10-08 05:32:03 -07:00
jcirimel d40c3588ed no wl for col end 2020-10-08 03:34:16 -07:00
jcirimel 4a1a7e637e merge in dev 2020-10-07 11:54:07 -07:00
jcirimel 888646cdf9 merge in wlbuf and begin work on 32kb memory 2020-10-06 05:03:59 -07:00
mrg a145a37cf7 PEP8 fixes in regress.py 2020-10-05 15:56:12 -07:00
mrg da83824a70 Merge branch 'wlbuffer' into dev 2020-10-05 15:33:54 -07:00
mrg c4952ca8be Skip full sram pex test too slow 2020-10-05 13:51:20 -07:00
mrg 4a58f09c1c Use 4x16 decoder with dual port bitcell in tests. 2020-10-05 10:52:56 -07:00
mrg c06b02e6fc Rename single_level_column_mux to just column_mux 2020-10-05 08:56:51 -07:00
mrg f8146e3f69 Add decoder4x16 2020-10-02 15:52:09 -07:00
mrg 64cc620440 Add sram pex test 2020-10-02 14:55:10 -07:00
mrg 1fc4040607 Add pand4 and pnand4 2020-10-02 14:54:12 -07:00
mrg a62b82128c Skip riscv func test because too slow 2020-10-02 13:33:58 -07:00
mrg 1e24b780bb Initial pex sram test. 2020-10-02 13:32:52 -07:00
mrg b32c123dab PEP8 cleanup. Un-hard-code bitcell layers. Remove dead variable. 2020-10-01 11:10:18 -07:00
Matt Guthaus 112d57d90a Enable riscv tests 2020-09-30 12:39:40 -07:00
mrg f4e6a8895b Update riscv unit test 2020-09-30 08:50:58 -07:00
jcirimel 7cbf456a4f sky130 rba done 2020-09-30 07:34:05 -07:00
mrg b147e8485c PEP8 formatting 2020-09-29 16:52:27 -07:00
mrg 8e908f016e PEP8 formatting 2020-09-29 13:43:59 -07:00
mrg 54890a8d77 Add new golden data 2020-09-29 13:43:34 -07:00
mrg 0c280e062a Fix func test with row/col of 0. PEP8 cleanup. Smaller global test case. 2020-09-29 11:35:58 -07:00
mrg 9032bb9869 Add global wordline delay test 2020-09-29 10:28:57 -07:00
mrg 1eb8798bb6 Add global functional test 2020-09-28 16:12:09 -07:00