Jesse Cirimelli-Low
11fa0777e8
add flatglob to tech file; sky130 replica col lvs working
2022-08-22 15:30:11 -07:00
mrg
d92c7a634d
Use packages for imports.
...
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
2022-07-13 15:55:57 -07:00
Jesse Cirimelli-Low
374562f354
rbc substrate issues
2022-06-16 15:17:07 -07:00
Jesse Cirimelli-Low
98fe4c74a4
colend fixes in progress
2022-06-15 22:34:21 -07:00
mrg
bbfccd1e00
Remove netlist bl/br swaps on flipped cells
2022-05-23 17:16:36 -07:00
Jesse Cirimelli-Low
825ada8293
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
2022-05-19 21:51:13 -07:00
Jesse Cirimelli-Low
172d070880
fix bl routing in rba
2022-05-19 21:45:48 -07:00
mrg
25fa0a8de3
Fix missing cell syntax error.
2022-05-19 14:53:17 -07:00
mrg
bdd334bce9
Add layer and directions to pbitcell
2022-05-16 16:11:13 -07:00
mrg
7195d81736
Adjust WL and GND for contacted via2 spacing.
2022-04-19 10:32:37 -07:00
mrg
64f2f90664
Rework replica_bitcell_array supplies
...
Uses layer and direction preferences in tech file.
Places straps on left/right or top/bottom.
2022-04-19 08:50:11 -07:00
mrg
68d0a56423
Fix WL to gnd spacing for grounded wordlines.
2022-04-04 16:02:47 -07:00
mrg
111533f0b0
Move power pins to horizontal or vertical layer in all cells.
2022-03-31 16:36:19 -07:00
mrg
83e5848728
Change FreePDK and SCMOS 2rw cell to share gnd power rail.
2022-03-30 13:48:53 -07:00
mrg
229a3b5b3d
By default uniquify instances based on macro name.
2022-03-11 18:01:45 -08:00
mrg
b75856fac9
Merge branch 'dev' into sky130_fixes
2022-03-09 11:31:42 -08:00
Jesse Cirimelli-Low
0667a93d53
single port rba passing lvs
2022-03-07 13:45:50 -08:00
Jesse Cirimelli-Low
038acd1568
single port rba lvs progress
2022-03-07 01:20:59 -08:00
mrg
67b51ff7f5
Move vdd pin in freepdk45 sense amp from dout
2022-03-06 12:20:54 -08:00
mrg
f7e3672c89
Route horizontal supplies in write driver.
2022-03-01 14:37:51 -08:00
mrg
9b90a44d4a
Move output in freepdk45 sense amp down to prevent router conflict with supply
2022-02-25 16:20:47 -08:00
mrg
12a6f1f2ee
Add missing well tap
2022-02-25 10:44:40 -08:00
mrg
049751ae1f
FreePDK45 running with klayout and Sky130 running with magic.
2022-02-03 10:19:28 -08:00
mrg
63a6168b35
Merge branch 'dev' into klayout
2022-02-01 11:57:56 -08:00
mrg
aeb9594877
Do not extract bb (bounding box) layer in SCN4M_SUBM tech file
2022-01-13 14:39:34 -08:00
mrg
e90ea4e737
Remove label Q_bar from replica_cell_1rw due to Magic port bug
2022-01-13 14:38:59 -08:00
mrg
47690e0076
Merge branch 'dev' into docker
2021-12-29 14:42:32 -08:00
Jesse Cirimelli-Low
8d9166a01b
only rba lvs errors is colend body extraction
2021-12-29 12:43:02 -08:00
Jesse Cirimelli-Low
9e85d17fbe
merge rbc lvs fixes
2021-12-23 21:21:10 -08:00
Jesse Cirimelli-Low
cf8c486cea
merge sky130_dummy_array
2021-12-22 16:00:59 -08:00
Jesse Cirimelli-Low
de60a1c38a
merge in opc fixes
2021-12-22 15:53:36 -08:00
Jesse Cirimelli-Low
468de963f6
remove add_mod in sky130
2021-12-22 15:51:49 -08:00
Jesse Cirimelli-Low
c24c37a15a
Merge branch 'dev' into lvs
2021-12-22 15:46:09 -08:00
Jesse Cirimelli-Low
8a0450afac
adjust replica col wls
2021-12-22 15:46:03 -08:00
mrg
e6e9d09369
Remove add_mod from sky130 modules
2021-12-17 10:30:55 -08:00
mrg
02364c6cdf
Add klayout option in config. No tool specific LVS libs
2021-12-17 10:29:17 -08:00
mrg
d555e67fb1
Add initial sky130 LVS/DRC rules.
2021-12-17 10:27:13 -08:00
Jesse Cirimelli-Low
8879820af4
replica col lvs fix
2021-12-15 14:19:52 -08:00
Jesse Cirimelli-Low
4e5744df50
remove add_mod()
2021-12-15 01:36:56 -08:00
Jesse Cirimelli-Low
99981109e8
Merge branch 'dev' into opc_fix
2021-12-15 01:31:21 -08:00
Jesse Cirimelli-Low
ddb76c4aff
fix dummy array opc
2021-12-15 01:28:30 -08:00
Jesse Cirimelli-Low
8eb6caa248
fix bitcell array opc errors
2021-12-14 22:15:27 -08:00
mrg
d8d8636d0f
Comment out calibre in freepdk45
2021-11-22 15:54:22 -08:00
mrg
66c9501621
Remove klayout from scmos
2021-11-22 11:33:27 -08:00
mrg
fc0516460d
Use klayout in SCMOS too.
2021-11-22 11:33:27 -08:00
mrg
32c7e90662
Do not run same well spacing for backwards compatibility. Add pbitcell cheat.
2021-11-22 11:33:27 -08:00
mrg
48e35588f4
Fix cheat on wordline driver name.
2021-11-22 11:33:27 -08:00
mrg
bfb33ecbb4
Add DRC rules and display files
2021-11-22 11:33:27 -08:00
mrg
779d6ad2b2
Debugging klayout for SCMOS and FreePDK45.
2021-11-22 11:33:27 -08:00
mrg
0c3ee643ab
Remove add_mod and add module whenever calling add_inst.
2021-11-22 11:33:27 -08:00
Jesse Cirimelli-Low
mrg