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rbc substrate issues

This commit is contained in:
Jesse Cirimelli-Low 2022-06-16 15:17:07 -07:00
parent c479915c02
commit 374562f354
3 changed files with 31 additions and 27 deletions
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10
technology/sky130/modules/sky130_col_cap_array.py
View File

@ -135,7 +135,7 @@ class sky130_col_cap_array(sky130_bitcell_base_array):
for fake_bl in range(self.cols):
self.add_pin("fake_bl_{}".format(fake_bl), "OUTPUT")
self.add_pin("fake_br_{}".format(fake_bl), "OUTPUT")
self.add_pin("fake_wl", "INPUT")
#self.add_pin("fake_wl", "INPUT")
self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND")
self.add_pin("gate", "BIAS")
@ -150,26 +150,26 @@ class sky130_col_cap_array(sky130_bitcell_base_array):
for pin in inst.get_pins(pin_name):
if inst.mod.cell_name == 'sky130_fd_bd_sram__sram_sp_colend' or 'sky130_fd_bd_sram__sram_sp_colenda':
if inst.mirror == "MY":
if pin_name == "vdd":
if pin_name == "vdd" and pin.layer == 'm1':
self.add_layout_pin_rect_center(text="vdd",
layer=pin.layer,
offset=inst.lr(),
width=pin.width(),
height=pin.height())
elif pin_name == "gnd":
elif pin_name == "gnd" and pin.layer == 'm1':
self.add_layout_pin_rect_center(text="gnd",
layer=pin.layer,
offset=inst.ll(),
width=pin.width(),
height=pin.height())
else:
if pin_name == "vdd":
if pin_name == "vdd" and pin.layer == 'm1':
self.add_layout_pin_rect_center(text="vdd",
layer=pin.layer,
offset=inst.ll(),
width=pin.width(),
height=pin.height())
elif pin_name == "gnd":
elif pin_name == "gnd" and pin.layer == 'm1':
self.add_layout_pin_rect_center(text="gnd",
layer=pin.layer,
offset=inst.lr(),

4
technology/sky130/modules/sky130_replica_bitcell_array.py
View File

@ -407,10 +407,10 @@ class sky130_replica_bitcell_array(replica_bitcell_array, sky130_bitcell_base_ar
self.dummy_row_insts = []
self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot",
mod=self.col_cap_bottom))
self.connect_inst(self.all_bitline_names + ["gnd"] * len(self.col_cap_bottom.get_wordline_names()) + self.supplies + ["gnd"])
self.connect_inst(self.all_bitline_names + self.supplies + ["gnd"])
self.dummy_row_insts.append(self.add_inst(name="dummy_row_top",
mod=self.col_cap_top))
self.connect_inst(self.all_bitline_names + ["gnd"] * len(self.col_cap_top.get_wordline_names()) + self.supplies + ["gnd"])
self.connect_inst(self.all_bitline_names + self.supplies + ["gnd"])
# Left/right Dummy columns
self.dummy_col_insts = []

44
technology/sky130/modules/sky130_replica_column.py
View File

@ -225,28 +225,32 @@ class sky130_replica_column(sky130_bitcell_base_array):
# add only 1 label per col
for pin_name in ["vdd", "gnd"]:
self.copy_layout_pin(inst, pin_name)
if row == 2:
if 'VPB' or 'vpb' in self.cell_inst[row].mod.pins:
pin = inst.get_pin("vpb")
self.objs.append(geometry.rectangle(layer["nwell"],
pin.ll(),
pin.width(),
pin.height()))
self.objs.append(geometry.label("vdd", layer["nwell"], pin.center()))
#if row == 2:
if 'VPB' or 'vpb' in self.cell_inst[row].mod.pins:
pin = inst.get_pin("vpb")
self.objs.append(geometry.rectangle(layer["nwell"],
pin.ll(),
pin.width(),
pin.height()))
self.objs.append(geometry.label("vdd", layer["nwell"], pin.center()))
if 'VNB' or 'vnb' in self.cell_inst[row].mod.pins:
try:
from tech import layer_override
if layer_override['VNB']:
pin = inst.get_pin("vnb")
self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center()))
self.objs.append(geometry.rectangle(layer["pwellp"],
pin.ll(),
pin.width(),
pin.height()))
except:
if 'VNB' or 'vnb' in self.cell_inst[row].mod.pins:
print("welling")
try:
from tech import layer_override
if layer_override['VNB']:
pin = inst.get_pin("vnb")
self.add_label("vdd", pin.layer, pin.center())
self.add_label("gnd", pin.layer, pin.center())
self.objs.append(geometry.rectangle(layer["pwellp"],
pin.ll(),
pin.width(),
pin.height()))
self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center()))
except:
pin = inst.get_pin("vnb")
self.add_label("gnd", pin.layer, pin.center())
def exclude_all_but_replica(self):
"""