mirror of https://github.com/VLSIDA/OpenRAM.git
fix bl routing in rba
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b75856fac9
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172d070880
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@ -167,8 +167,8 @@ class sky130_bitcell_base_array(bitcell_base_array):
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for port in self.all_ports:
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bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
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text = "bl_{0}_{1}".format(port, col)
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if "Y" in self.cell_inst[0, col].mirror:
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text = text.replace("bl", "br")
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#if "Y" in self.cell_inst[0, col].mirror:
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# text = text.replace("bl", "br")
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self.add_layout_pin(text=text,
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layer=bl_pin.layer,
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offset=bl_pin.ll().scale(1, 0),
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@ -176,8 +176,8 @@ class sky130_bitcell_base_array(bitcell_base_array):
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height=self.height)
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br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
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text = "br_{0}_{1}".format(port, col)
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if "Y" in self.cell_inst[0, col].mirror:
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text = text.replace("br", "bl")
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#if "Y" in self.cell_inst[0, col].mirror:
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# text = text.replace("br", "bl")
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self.add_layout_pin(text=text,
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layer=br_pin.layer,
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offset=br_pin.ll().scale(1, 0),
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@ -325,16 +325,16 @@ class sky130_replica_bitcell_array(replica_bitcell_array, sky130_bitcell_base_ar
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for (bl_name, pin_name) in zip(names, pin_names):
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pin = inst.get_pin(pin_name)
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if 'rbl_bl' in bl_name:
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if mirror != "MY":
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bl_name = bl_name.replace("rbl_bl","rbl_br")
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# if mirror != "MY":
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# bl_name = bl_name.replace("rbl_bl","rbl_br")
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self.add_layout_pin(text=bl_name,
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layer=pin.layer,
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offset=pin.ll().scale(1, 0),
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width=pin.width(),
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height=self.height)
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elif 'rbl_br' in bl_name:
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if mirror != "MY":
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bl_name = bl_name.replace("rbl_br","rbl_bl")
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# if mirror != "MY":
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# bl_name = bl_name.replace("rbl_br","rbl_bl")
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self.add_layout_pin(text=bl_name,
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layer=pin.layer,
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offset=pin.ll().scale(1, 0) + vector(0,(pin_height + drc_width*2)),
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