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luke
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OpenRAM
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https://github.com/VLSIDA/OpenRAM.git
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2026-08-29 01:24:39 +02:00
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83e5848728fa95fc231aadb80d5f3888154773d7
OpenRAM
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technology
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mrg
83e5848728
Change FreePDK and SCMOS 2rw cell to share gnd power rail.
2022-03-30 13:48:53 -07:00
..
freepdk45
Change FreePDK and SCMOS 2rw cell to share gnd power rail.
2022-03-30 13:48:53 -07:00
scn3me_subm
add dimension contraints to other tech files
2021-06-18 14:36:15 -07:00
scn4m_subm
Change FreePDK and SCMOS 2rw cell to share gnd power rail.
2022-03-30 13:48:53 -07:00
setup_scripts
Moved model scripts to characterizer dir
2020-12-02 13:25:03 -08:00
sky130
single port rba passing lvs
2022-03-07 13:45:50 -08:00