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Remove netlist bl/br swaps on flipped cells

This commit is contained in:
mrg 2022-05-23 17:16:36 -07:00
parent aed2ef4ecc
commit bbfccd1e00
4 changed files with 6 additions and 25 deletions
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5
technology/sky130/modules/sky130_bitcell_array.py
View File

@ -63,10 +63,7 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array):
row_layout.append(self.cell2)
self.cell_inst[row, col]=self.add_inst(name="row_{}_col_{}_bitcell".format(row, col),
mod=self.cell2)
if col % 2 == 1:
self.connect_inst(self.get_bitcell_pins(row, col, swap=True))
else:
self.connect_inst(self.get_bitcell_pins(row, col, swap=False))
self.connect_inst(self.get_bitcell_pins(row, col))
if col != self.column_size - 1:
if alternate_strap:
if row % 2:

8
technology/sky130/modules/sky130_bitcell_base_array.py
View File

@ -69,14 +69,6 @@ class sky130_bitcell_base_array(bitcell_base_array):
bitcell_pins = []
for port in self.all_ports:
bitcell_pins.extend([x for x in self.get_bitline_names(port) if x.endswith("_{0}".format(col))])
if swap:
swap_pins = []
for pin in bitcell_pins:
if "bl" in pin:
swap_pins.append(pin.replace("bl", "br"))
elif "br" in pin:
swap_pins.append(pin.replace("br", "bl"))
bitcell_pins = swap_pins
bitcell_pins.append("gnd") # gnd
bitcell_pins.append("vdd") # vdd
bitcell_pins.append("vdd") # vpb

8
technology/sky130/modules/sky130_col_cap_array.py
View File

@ -89,10 +89,10 @@ class sky130_col_cap_array(sky130_bitcell_base_array):
elif col % 4 == 2:
row_layout.append(self.colend1)
self.cell_inst[col]=self.add_inst(name=name, mod=self.colend1)
pins.append("fake_br_{}".format(bitline))
pins.append("fake_bl_{}".format(bitline))
pins.append("vdd")
pins.append("gnd")
pins.append("fake_bl_{}".format(bitline))
pins.append("fake_br_{}".format(bitline))
pins.append("gate")
bitline += 1
elif col % 4 ==3:
@ -194,7 +194,7 @@ class sky130_col_cap_array(sky130_bitcell_base_array):
elif col % 4 == 2:
pin = self.cell_inst[col].get_pin("bl")
text = "fake_br_{}".format(int(col/2))
text = "fake_bl_{}".format(int(col/2))
self.add_layout_pin(text=text,
layer=pin.layer,
offset=pin.ll().scale(1, 0),
@ -202,7 +202,7 @@ class sky130_col_cap_array(sky130_bitcell_base_array):
height=pin.height())
pin = self.cell_inst[col].get_pin("br")
text = "fake_bl_{}".format(int(col/2))
text = "fake_br_{}".format(int(col/2))
self.add_layout_pin(text=text,
layer=pin.layer,
offset=pin.ll().scale(1, 0),

10
technology/sky130/modules/sky130_dummy_array.py
View File

@ -72,11 +72,7 @@ class sky130_dummy_array(sky130_bitcell_base_array):
row_layout.append(self.dummy_cell2)
self.cell_inst[row, col]=self.add_inst(name="row_{}_col_{}_bitcell".format(row, col),
mod=self.dummy_cell2)
if col % 2 == 1:
self.connect_inst(self.get_bitcell_pins(row, col, swap=True))
else:
self.connect_inst(self.get_bitcell_pins(row, col, swap=False))
#self.connect_inst(self.get_bitcell_pins(row, col))
self.connect_inst(self.get_bitcell_pins(row, col))
if col != self.column_size - 1:
if alternate_strap:
if col % 2:
@ -129,8 +125,6 @@ class sky130_dummy_array(sky130_bitcell_base_array):
for port in self.all_ports:
bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
text = "bl_{0}_{1}".format(port, col)
if "Y" in self.cell_inst[0, col].mirror:
text = text.replace("bl", "br")
self.add_layout_pin(text=text,
layer=bl_pin.layer,
offset=bl_pin.ll().scale(1, 0),
@ -138,8 +132,6 @@ class sky130_dummy_array(sky130_bitcell_base_array):
height=self.height)
br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
text = "br_{0}_{1}".format(port, col)
if "Y" in self.cell_inst[0, col].mirror:
text = text.replace("br", "bl")
self.add_layout_pin(text=text,
layer=br_pin.layer,
offset=br_pin.ll().scale(1, 0),