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Rework replica_bitcell_array supplies

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Uses layer and direction preferences in tech file.
Places straps on left/right or top/bottom.
This commit is contained in:
mrg
2022-04-19 08:50:11 -07:00
parent 5e546ee974
commit 64f2f90664
11 changed files with 210 additions and 61 deletions
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technology/freepdk45/tech/tech.py
-1
View File
@@ -31,7 +31,6 @@ tech_modules = module_type()
# Custom cell properties
###################################################
cell_properties = cell_properties()
cell_properties.bitcell_power_pin_directions = ("V", "V")
###################################################
# Custom cell properties
technology/scn4m_subm/tech/tech.py
+2
View File
@@ -30,6 +30,8 @@ tech_modules = module_type()
# Custom cell properties
###################################################
cell_properties = cell_properties()
cell_properties.bitcell_1port.gnd_layer = "m2"
cell_properties.bitcell_1port.gnd_dir = "V"
###################################################
# Custom cell properties
technology/sky130/tech/tech.py
+17
View File
@@ -86,6 +86,13 @@ cell_properties.bitcell_1port.port_map = {'bl': 'BL',
'vpb': 'VPB',
'gnd': 'VGND'}
cell_properties.bitcell_1port.wl_layer = "m2"
cell_properties.bitcell_1port.bl_layer = "m1"
cell_properties.bitcell_1port.vdd_layer = "m1"
cell_properties.bitcell_1port.vdd_dir = "V"
cell_properties.bitcell_1port.gnd_layer = "m2"
cell_properties.bitcell_1port.gnd_dir = "H"
cell_properties.bitcell_2port.mirror.x = True
cell_properties.bitcell_2port.mirror.y = True
cell_properties.bitcell_2port.end_caps = True
@@ -98,6 +105,16 @@ cell_properties.bitcell_2port.port_map = {'bl0': 'BL0',
'wl1': 'WL1',
'vdd': 'VDD',
'gnd': 'GND'}
cell_properties.bitcell_1port.wl_layer = "m2"
cell_properties.bitcell_1port.vdd_layer = "m2"
cell_properties.bitcell_1port.vdd_dir = "H"
cell_properties.bitcell_1port.gnd_layer = "m2"
cell_properties.bitcell_1port.gnd_dir = "H"
cell_properties.bitcell_2port.wl_layer = "m2"
cell_properties.bitcell_2port.vdd_layer = "m1"
cell_properties.bitcell_2port.vdd_dir = "H"
cell_properties.bitcell_2port.gnd_layer = "m2"
cell_properties.bitcell_2port.gnd_dir = "H"
cell_properties.col_cap_1port_bitcell = cell(['br', 'vdd', 'gnd', 'bl', 'gate'],
['INPUT', 'POWER', 'GROUND', 'INPUT', 'INPUT'],