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colend fixes in progress

This commit is contained in:
Jesse Cirimelli-Low 2022-06-15 22:34:21 -07:00
parent 69bb6826dc
commit 98fe4c74a4
5 changed files with 36 additions and 27 deletions
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5
technology/sky130/modules/sky130_bitcell_base_array.py
View File

@ -107,6 +107,7 @@ class sky130_bitcell_base_array(bitcell_base_array):
strap_pins.extend(["top_gate"])
else:
strap_pins.extend(["bot_gate"])
strap_pins.extend(["vdd", "gnd"])
return strap_pins
def get_row_cap_pins(self, row, col):
@ -131,7 +132,7 @@ class sky130_bitcell_base_array(bitcell_base_array):
self.copy_layout_pin(inst, pin_name)
if row == 2: #add only 1 label per col
if 'VPB' in self.cell_inst[row, col].mod.pins:
if 'VPB' or 'vpb' in self.cell_inst[row, col].mod.pins:
pin = inst.get_pin("vpb")
self.objs.append(geometry.rectangle(layer["nwell"],
pin.ll(),
@ -139,7 +140,7 @@ class sky130_bitcell_base_array(bitcell_base_array):
pin.height()))
self.objs.append(geometry.label("vdd", layer["nwell"], pin.center()))
if 'VNB' in self.cell_inst[row, col].mod.pins:
if 'VNB' or 'vnb'in self.cell_inst[row, col].mod.pins:
try:
from tech import layer_override
if layer_override['VNB']:

34
technology/sky130/modules/sky130_col_cap_array.py
View File

@ -42,7 +42,7 @@ class sky130_col_cap_array(sky130_bitcell_base_array):
self.place_array("dummy_r{0}_c{1}", self.mirror)
self.add_layout_pins()
#self.add_supply_pins()
self.add_supply_pins()
self.add_boundary()
self.DRC_LVS()
@ -79,6 +79,8 @@ class sky130_col_cap_array(sky130_bitcell_base_array):
pins.append("gnd")
pins.append("fake_br_{}".format(bitline))
pins.append("gate")
pins.append("vdd")
pins.append("gnd")
bitline += 1
elif col % 4 == 1:
row_layout.append(self.colend2)
@ -94,6 +96,8 @@ class sky130_col_cap_array(sky130_bitcell_base_array):
pins.append("gnd")
pins.append("fake_br_{}".format(bitline))
pins.append("gate")
pins.append("vdd")
pins.append("gnd")
bitline += 1
elif col % 4 ==3:
row_layout.append(self.colend2)
@ -136,6 +140,7 @@ class sky130_col_cap_array(sky130_bitcell_base_array):
self.add_pin("gnd", "GROUND")
self.add_pin("gate", "BIAS")
def add_layout_pins(self):
""" Add the layout pins """
# Add vdd/gnd via stacks
@ -208,35 +213,36 @@ class sky130_col_cap_array(sky130_bitcell_base_array):
offset=pin.ll().scale(1, 0),
width=pin.width(),
height=pin.height())
return
def add_supply_pins(self):
for col in range(self.cols):
for col in range(len(self.insts)):
inst = self.cell_inst[col]
if 'VPB' in self.cell_inst[col].mod.pins:
if 'VPB' or 'vnb' in self.cell_inst[col].mod.pins:
pin = inst.get_pin("vpb")
self.objs.append(geometry.rectangle(layer["nwell"],
pin.ll(),
pin.width(),
pin.height()))
pin.ll(),
pin.width(),
pin.height()))
self.objs.append(geometry.label("vdd", layer["nwell"], pin.center()))
if 'VNB' in self.cell_inst[col].mod.pins:
if 'VNB' or 'vnb' in self.cell_inst[col].mod.pins:
try:
from tech import layer_override
if layer_override['VNB']:
pin = inst.get_pin("vnb")
self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center()))
self.objs.append(geometry.rectangle(layer["pwellp"],
pin.ll(),
pin.width(),
pin.height()))
pin.ll(),
pin.width(),
pin.height()))
except:
pin = inst.get_pin("vnb")
self.add_label("vdd", pin.layer, pin.center())
def create_all_wordline_names(self, row_size=None):
if row_size == None:

4
technology/sky130/modules/sky130_dummy_array.py
View File

@ -167,7 +167,7 @@ class sky130_dummy_array(sky130_bitcell_base_array):
for row in range(self.row_size):
for col in range(self.column_size):
inst = self.cell_inst[row, col]
if 'VPB' in self.cell_inst[row, col].mod.pins:
if 'VPB' or 'vpb' in self.cell_inst[row, col].mod.pins:
pin = inst.get_pin("vpb")
self.objs.append(geometry.rectangle(layer["nwell"],
pin.ll(),
@ -175,7 +175,7 @@ class sky130_dummy_array(sky130_bitcell_base_array):
pin.height()))
self.objs.append(geometry.label("vdd", layer["nwell"], pin.center()))
if 'VNB' in self.cell_inst[row, col].mod.pins:
if 'VNB' or 'vnb' in self.cell_inst[row, col].mod.pins:
try:
from tech import layer_override
if layer_override['VNB']:

4
technology/sky130/modules/sky130_replica_column.py
View File

@ -226,7 +226,7 @@ class sky130_replica_column(sky130_bitcell_base_array):
for pin_name in ["vdd", "gnd"]:
self.copy_layout_pin(inst, pin_name)
if row == 2:
if 'VPB' in self.cell_inst[row].mod.pins:
if 'VPB' or 'vpb' in self.cell_inst[row].mod.pins:
pin = inst.get_pin("vpb")
self.objs.append(geometry.rectangle(layer["nwell"],
pin.ll(),
@ -234,7 +234,7 @@ class sky130_replica_column(sky130_bitcell_base_array):
pin.height()))
self.objs.append(geometry.label("vdd", layer["nwell"], pin.center()))
if 'VNB' in self.cell_inst[row].mod.pins:
if 'VNB' or 'vnb' in self.cell_inst[row].mod.pins:
try:
from tech import layer_override
if layer_override['VNB']:

16
technology/sky130/tech/tech.py
View File

@ -116,13 +116,15 @@ cell_properties.bitcell_2port.vdd_dir = "H"
cell_properties.bitcell_2port.gnd_layer = "m2"
cell_properties.bitcell_2port.gnd_dir = "H"
cell_properties.col_cap_1port_bitcell = cell(['br', 'vdd', 'gnd', 'bl', 'gate'],
['INPUT', 'POWER', 'GROUND', 'INPUT', 'INPUT'],
{'bl': 'BL0',
'br': 'BL1',
'vdd': 'VPWR',
'gnd': 'VGND',
'gate': 'gate'})
cell_properties.col_cap_1port_bitcell = cell(['bl', 'vdd', 'gnd', 'br', 'gate', 'vpb', 'vnb'],
['INPUT', 'POWER', 'GROUND', 'INPUT', 'INPUT', 'BIAS', 'BIAS'],
{'bl': 'bl',
'br': 'br',
'vdd': 'vdd',
'gnd': 'gnd',
'gate': 'gate',
'vnb': 'vnb',
'vpb': 'vpb'})
cell_properties.col_cap_1port_bitcell.boundary_layer = "mem"
cell_properties.col_cap_1port_strap_power = cell(['vdd', 'vpb', 'vnb'],