mirror of https://github.com/VLSIDA/OpenRAM.git
Merge branch 'dev' into sky130_fixes
This commit is contained in:
mrg
commit
b75856fac9
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@ -63,8 +63,10 @@ class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array):
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row_layout.append(self.cell2)
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self.cell_inst[row, col]=self.add_inst(name="row_{}_col_{}_bitcell".format(row, col),
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mod=self.cell2)
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self.connect_inst(self.get_bitcell_pins(row, col))
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if col % 2 == 1:
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self.connect_inst(self.get_bitcell_pins(row, col, swap=True))
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else:
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self.connect_inst(self.get_bitcell_pins(row, col, swap=False))
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if col != self.column_size - 1:
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if alternate_strap:
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if row % 2:
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@ -61,7 +61,7 @@ class sky130_bitcell_base_array(bitcell_base_array):
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self.width = max([x.rx() for x in self.insts])
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self.height = max([x.uy() for x in self.insts])
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def get_bitcell_pins(self, row, col):
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def get_bitcell_pins(self, row, col, swap = False):
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"""
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Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array
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@ -69,6 +69,14 @@ class sky130_bitcell_base_array(bitcell_base_array):
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bitcell_pins = []
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for port in self.all_ports:
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bitcell_pins.extend([x for x in self.get_bitline_names(port) if x.endswith("_{0}".format(col))])
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if swap:
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swap_pins = []
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for pin in bitcell_pins:
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if "bl" in pin:
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swap_pins.append(pin.replace("bl", "br"))
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elif "br" in pin:
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swap_pins.append(pin.replace("br", "bl"))
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bitcell_pins = swap_pins
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bitcell_pins.append("gnd") # gnd
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bitcell_pins.append("vdd") # vdd
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bitcell_pins.append("vdd") # vpb
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@ -104,9 +112,9 @@ class sky130_bitcell_base_array(bitcell_base_array):
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for port in self.all_ports:
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strap_pins.extend([x for x in self.get_bitline_names(port) if "br" in x and x.endswith("_{0}".format(col))])
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if row == 0:
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strap_pins.extend(["gate_top"])
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strap_pins.extend(["top_gate"])
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else:
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strap_pins.extend(["gate_bottom"])
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strap_pins.extend(["bot_gate"])
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return strap_pins
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def get_row_cap_pins(self, row, col):
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@ -152,3 +160,26 @@ class sky130_bitcell_base_array(bitcell_base_array):
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except:
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pin = inst.get_pin("vnb")
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self.add_label("vdd", pin.layer, pin.center())
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def add_bitline_pins(self):
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bitline_names = self.cell.get_all_bitline_names()
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for col in range(self.column_size):
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for port in self.all_ports:
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bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
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text = "bl_{0}_{1}".format(port, col)
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if "Y" in self.cell_inst[0, col].mirror:
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text = text.replace("bl", "br")
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self.add_layout_pin(text=text,
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layer=bl_pin.layer,
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offset=bl_pin.ll().scale(1, 0),
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width=bl_pin.width(),
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height=self.height)
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br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
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text = "br_{0}_{1}".format(port, col)
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if "Y" in self.cell_inst[0, col].mirror:
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text = text.replace("br", "bl")
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self.add_layout_pin(text=text,
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layer=br_pin.layer,
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offset=br_pin.ll().scale(1, 0),
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width=br_pin.width(),
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height=self.height)
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@ -89,10 +89,10 @@ class sky130_col_cap_array(sky130_bitcell_base_array):
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elif col % 4 == 2:
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row_layout.append(self.colend1)
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self.cell_inst[col]=self.add_inst(name=name, mod=self.colend1)
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pins.append("fake_bl_{}".format(bitline))
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pins.append("fake_br_{}".format(bitline))
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pins.append("vdd")
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pins.append("gnd")
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pins.append("fake_br_{}".format(bitline))
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pins.append("fake_bl_{}".format(bitline))
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pins.append("gate")
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bitline += 1
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elif col % 4 ==3:
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@ -170,6 +170,48 @@ class sky130_col_cap_array(sky130_bitcell_base_array):
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offset=inst.lr(),
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width=pin.width(),
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height=pin.height())
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for col in range(len(self.insts)):
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inst = self.insts[col]
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if col % 4 == 0:
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pin = self.cell_inst[col].get_pin("bl")
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text = "fake_bl_{}".format(int(col/2))
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self.add_layout_pin(text=text,
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layer=pin.layer,
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offset=pin.ll().scale(1, 0),
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width=pin.width(),
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height=pin.height())
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pin = self.cell_inst[col].get_pin("br")
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text = "fake_br_{}".format(int(col/2))
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self.add_layout_pin(text=text,
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layer=pin.layer,
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offset=pin.ll().scale(1, 0),
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width=pin.width(),
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height=pin.height())
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elif col % 4 == 2:
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pin = self.cell_inst[col].get_pin("bl")
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text = "fake_br_{}".format(int(col/2))
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self.add_layout_pin(text=text,
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layer=pin.layer,
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offset=pin.ll().scale(1, 0),
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width=pin.width(),
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height=pin.height())
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pin = self.cell_inst[col].get_pin("br")
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text = "fake_bl_{}".format(int(col/2))
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self.add_layout_pin(text=text,
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layer=pin.layer,
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offset=pin.ll().scale(1, 0),
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width=pin.width(),
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height=pin.height())
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return
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def add_supply_pins(self):
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@ -72,8 +72,11 @@ class sky130_dummy_array(sky130_bitcell_base_array):
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row_layout.append(self.dummy_cell2)
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self.cell_inst[row, col]=self.add_inst(name="row_{}_col_{}_bitcell".format(row, col),
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mod=self.dummy_cell2)
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self.connect_inst(self.get_bitcell_pins(row, col))
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if col % 2 == 1:
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self.connect_inst(self.get_bitcell_pins(row, col, swap=True))
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else:
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self.connect_inst(self.get_bitcell_pins(row, col, swap=False))
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#self.connect_inst(self.get_bitcell_pins(row, col))
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if col != self.column_size - 1:
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if alternate_strap:
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if col % 2:
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@ -99,6 +102,7 @@ class sky130_dummy_array(sky130_bitcell_base_array):
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self.add_inst(name=name,
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mod=self.strap3)
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alternate_strap = 1
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self.connect_inst(self.get_strap_pins(row, col, name))
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if alternate_bitcell == 0:
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alternate_bitcell = 1
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@ -108,11 +112,11 @@ class sky130_dummy_array(sky130_bitcell_base_array):
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def add_pins(self):
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# bitline pins are not added because they are floating
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for wl_name in self.get_wordline_names():
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self.add_pin(wl_name, "INPUT")
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for bl in range(self.column_size):
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self.add_pin("bl_0_{}".format(bl))
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self.add_pin("br_0_{}".format(bl))
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for wl_name in self.get_wordline_names():
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self.add_pin(wl_name, "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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#self.add_pin("vpb", "BIAS")
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@ -124,13 +128,19 @@ class sky130_dummy_array(sky130_bitcell_base_array):
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for col in range(self.column_size):
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for port in self.all_ports:
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bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
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self.add_layout_pin(text="bl_{0}_{1}".format(port, col),
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text = "bl_{0}_{1}".format(port, col)
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if "Y" in self.cell_inst[0, col].mirror:
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text = text.replace("bl", "br")
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self.add_layout_pin(text=text,
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layer=bl_pin.layer,
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offset=bl_pin.ll().scale(1, 0),
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width=bl_pin.width(),
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height=self.height)
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br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
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self.add_layout_pin(text="br_{0}_{1}".format(port, col),
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text = "br_{0}_{1}".format(port, col)
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if "Y" in self.cell_inst[0, col].mirror:
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text = text.replace("br", "bl")
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self.add_layout_pin(text=text,
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layer=br_pin.layer,
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offset=br_pin.ll().scale(1, 0),
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width=br_pin.width(),
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@ -321,15 +321,20 @@ class sky130_replica_bitcell_array(replica_bitcell_array, sky130_bitcell_base_ar
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if len(self.rbls) > 0:
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for (names, inst) in zip(self.rbl_bitline_names, self.replica_col_insts):
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pin_names = self.replica_columns[self.rbls[0]].all_bitline_names
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mirror = self.replica_col_insts[0].mirror
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for (bl_name, pin_name) in zip(names, pin_names):
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pin = inst.get_pin(pin_name)
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if 'rbl_bl' in bl_name:
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if mirror != "MY":
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bl_name = bl_name.replace("rbl_bl","rbl_br")
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self.add_layout_pin(text=bl_name,
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layer=pin.layer,
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offset=pin.ll().scale(1, 0),
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width=pin.width(),
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height=self.height)
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elif 'rbl_br' in bl_name:
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if mirror != "MY":
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bl_name = bl_name.replace("rbl_br","rbl_bl")
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self.add_layout_pin(text=bl_name,
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layer=pin.layer,
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offset=pin.ll().scale(1, 0) + vector(0,(pin_height + drc_width*2)),
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@ -90,8 +90,8 @@ class sky130_replica_column(sky130_bitcell_base_array):
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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self.add_pin("gate_top", "BIAS")
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self.add_pin("gate_bottom", "BIAS")
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self.add_pin("top_gate", "INPUT")
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self.add_pin("bot_gate", "INPUT")
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def add_modules(self):
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self.replica_cell = factory.create(module_type="replica_bitcell_1port", version="opt1")
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@ -214,7 +214,7 @@ class sky130_replica_column(sky130_bitcell_base_array):
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for port in self.all_ports:
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for row in range(row_range_min, row_range_max):
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wl_pin = self.cell_inst[row].get_pin(self.cell.get_wl_name(port))
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self.add_layout_pin(text="wl_{0}_{1}".format(port, row),
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self.add_layout_pin(text="wl_{0}_{1}".format(port, row_range_max-row),
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layer=wl_pin.layer,
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offset=wl_pin.ll().scale(0, 1),
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width=self.width,
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