 mrg
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da83824a70
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Merge branch 'wlbuffer' into dev
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2020-10-05 15:33:54 -07:00 |
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mrg
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4a58f09c1c
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Use 4x16 decoder with dual port bitcell in tests.
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2020-10-05 10:52:56 -07:00 |
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mrg
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c06b02e6fc
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Rename single_level_column_mux to just column_mux
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2020-10-05 08:56:51 -07:00 |
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mrg
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f8146e3f69
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Add decoder4x16
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2020-10-02 15:52:09 -07:00 |
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mrg
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8ce23d7f17
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Provide unique WL driver instance name
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2020-10-01 07:17:32 -07:00 |
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Matt Guthaus
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112d57d90a
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Enable riscv tests
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2020-09-30 12:39:40 -07:00 |
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mrg
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f4e6a8895b
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Update riscv unit test
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2020-09-30 08:50:58 -07:00 |
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mrg
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b147e8485c
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PEP8 formatting
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2020-09-29 16:52:27 -07:00 |
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mrg
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066570bfeb
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Fix length of write driver
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2020-09-29 16:51:55 -07:00 |
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mrg
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449a4c2660
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Exclude bitcells in other local areas not of interest
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2020-09-29 12:15:42 -07:00 |
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mrg
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d7e2340e62
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Lots of PEP8 cleanup. Refactor path graph to simulation class.
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2020-09-29 10:26:31 -07:00 |
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mrg
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b2dab486fc
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Add draft of path exclusion calls
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2020-09-28 16:05:21 -07:00 |
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mrg
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4a987bef9a
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Merge branch 'wlbuffer' into dev
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2020-09-28 15:51:45 -07:00 |
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mrg
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159c04a25d
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-09-28 15:51:35 -07:00 |
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mrg
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70c90ca7fb
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Replica bitcell array bbox to include unused WL gnd pins.
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2020-09-28 14:49:33 -07:00 |
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mrg
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9c6d8d7aed
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Zjob to bottom.
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2020-09-28 13:16:03 -07:00 |
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mrg
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5ab0d01779
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Remove zjog and go with L shape.
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2020-09-28 12:48:37 -07:00 |
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mrg
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d65eb16513
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Zjog the WL enable. Min driver is 1.
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2020-09-28 12:24:55 -07:00 |
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mrg
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6f06bb9dd5
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Create sized RBL WL driver in port_address
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2020-09-28 11:30:21 -07:00 |
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mrg
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88731ccd8e
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Fix rounding error for wmask with various word_size
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2020-09-28 09:53:01 -07:00 |
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mrg
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c7d32089f3
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Create RBL wordline buffer with correct polarity.
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2020-09-17 14:45:49 -07:00 |
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mrg
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e7ad22ff69
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Separate WL via from bitell array to avoid grounded WLs
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2020-09-15 13:38:28 -07:00 |
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mrg
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5e94d76127
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Make global bitline only as wide as needed rather than whole array
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2020-09-15 13:24:38 -07:00 |
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mrg
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aff3cd2aab
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Update length of control bus
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2020-09-15 09:49:00 -07:00 |
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mrg
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f25b6ffa61
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Make control bus height of port data
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2020-09-14 15:42:17 -07:00 |
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mrg
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7b24d1f012
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Use pins for write_driver dimensions
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2020-09-14 14:42:28 -07:00 |
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mrg
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55dd4d0c47
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Global bitcell array working
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2020-09-14 14:35:52 -07:00 |
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mrg
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deaaec1ede
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Fix width of write enable with spare columns
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2020-09-14 13:09:45 -07:00 |
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mrg
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c12720a93f
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Extend pin correct length in new array.
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2020-09-14 12:53:59 -07:00 |
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mrg
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e95ab66916
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Update to space according to the bitcell array.
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2020-09-14 12:05:45 -07:00 |
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mrg
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4482c63d6f
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Fix sense amp offset index error
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2020-09-11 17:12:29 -07:00 |
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mrg
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8909ad7165
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Update modules to use variable bit offsets.
Bitcell arrays can return the bit offsets.
Port data and submodules can use offsets for spacing.
Default spacing for port data if no offsets given.
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2020-09-11 15:36:22 -07:00 |
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mrg
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c58741c44f
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Updates to global array.
Standardize bitcell array main array offsets.
Duplicate replica interface pins in global interface pins.
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2020-09-10 16:44:54 -07:00 |
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mrg
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9c762634a5
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Change default options for replica_bitcell_array
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2020-09-10 15:11:48 -07:00 |
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mrg
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71d86f88b0
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Merge branch 'dev' into wlbuffer
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2020-09-10 13:05:14 -07:00 |
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mrg
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f2313d0c73
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Use default names for replica_column too
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2020-09-10 12:04:46 -07:00 |
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mrg
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3c0707e5d1
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Consistents of bl x port then br x port
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2020-09-09 13:38:13 -07:00 |
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mrg
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3062aba214
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Fix update to exclude bits with RBLs
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2020-09-09 13:03:05 -07:00 |
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mrg
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7bb21fb73f
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Updates to local and global arrays to make bitline and wordlines consistent.
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2020-09-09 11:54:46 -07:00 |
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mrg
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1269bf6e16
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Global bitcell working
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2020-09-04 13:06:58 -07:00 |
|
 Hunter Nichols
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8bcbf005bf
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Merge branch 'dev' into characterizer_bug_fixes
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2020-09-04 02:25:01 -07:00 |
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mrg
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1534295326
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Ground dummy lines in replica bitcell array
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2020-09-03 14:04:20 -07:00 |
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mrg
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f6f6242d68
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Ground dummy lines in replica bitcell array
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2020-09-03 10:45:28 -07:00 |
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mrg
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4ec47d8ee1
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Refactor global and local to be a bitcell_base_array
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2020-09-01 11:59:01 -07:00 |
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mrg
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c1c631abe1
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Global bitcell array passes LVS/DRC
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2020-09-01 10:57:49 -07:00 |
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mrg
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7bdce3ca9a
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Don't make dummy bitlines pins for simplicity
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2020-09-01 09:55:23 -07:00 |
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Hunter Nichols
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73b2277daa
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Removed dead code related to older characterization scheme
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2020-08-27 17:30:58 -07:00 |
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mrg
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c1c1535210
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Merge branch 'wlbuffer' into dev
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2020-08-27 15:44:29 -07:00 |
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mrg
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11a82b7283
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Fixed local bitcell array for single and dual port
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2020-08-27 14:03:05 -07:00 |
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mrg
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da827d923f
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Merge branch 'wlbuffer' into dev
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2020-08-26 10:00:34 -07:00 |
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